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high performance 8-bit display interface ad9980 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . specifications subjec t to chan g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2005 analog de vices, i n c. al l r i ght s r e ser v ed . features 95 msps maxi mum conversi on rate 9% or less p-p pll clock jitter at 95 msps automated offset adjustm e nt 2:1 input m u x power-down vi a dedicated pi n or serial regis t er 4:4:4, 4: 2:2, an d ddr output f o rmat modes variable output drive strengt h o dd/even fie l d detectio n external clock i n put regenerated hsync output programmable output high i m pedance control hsy n cs per vsyncs cou n ter pb-free packag e applic ati o ns advance d tv s plasma display panels lcd tv hdtv rgb graphics processing lcd monitors and projectors scan converters func tio n a l block di agram cb/cr/red out y/green out cb/blue out sync processing pll power management sogout o/e field hsout vsout/a0 voltage refs serial register sda scl filt clamp extclk/coas t hsync2 hsync1 ad9980 clamp 8 clamp 8 clamp 8 8 8 8 8 8 8 8-bit adc refhi refcm reflo dtack 04740- 013 auto offset auto offset auto offset ouput dat a f o rm at t e r 8-bit adc 8-bit adc pga pga pga 2:1 mux pr/red in 0 pr/red in 1 2:1 mux y/green in 0 y/green in 1 2:1 mux pb/blue in 0 pb/blue in 1 2:1 mux vsync2 vsync1 2:1 mux sogin2 sogin1 2:1 mux fi g u r e 1 . general description the ad9980 is a co m p lete , 8-b i t, 95 ms ps, m o n o li thic a n alog in ter f ace o p t i m i ze d fo r ca pt ur ing ypbpr v i de o and rgb g r a p hics sig n als . i t s 95 ms ps enco de ra t e c a p a b i li ty an d f u l l - p o w e r a n alog ba ndwid t h o f 200 mh z su p p o r ts al l hdt v video m o des and g r a p hics r e s o l u tio n s u p t o x g a (1024 768 a t 85 h z ). the ad9980 inc l udes a 95 mh z tr i p le ad c wi th a n in ter n al re f e re nc e, a p h a s e - l o c k e d l o op ( p l l ) , pro g r a m m a bl e g a i n , o f fs et, a n d cla m p co n t r o ls. th e us er p r o v ides o n l y 3.3 v a nd 1.8 v p o w e r s u p p l ies a nd an a n a l og in p u t. thr e e-s t a t e cm os o u t p u t s ma y be p o w e r e d f r o m 1.8 v t o 3.3 v . the ad9980 s on-c hi p p ll g e nera t e s a s a m p le c l o c k f r o m th e th r ee- lev e l syn c (f o r y p b p r v i d e o) o r th e h o ri z o n t al syn c ( f or rg b g r a p h i c s ) . s a m p l e cl o c k output f r e q u e nc i e s r a ng e f r om 10 mh z t o 95 mh z. p l l c l o c k ji t t er is 9 % o r les s p-p typ i cal a t 95 ms ps. w i t h in t e rn al c o a s t g e n e ra ti o n , th e pl l m a in ta i n s i t s o u t p u t f r e q uen c y in t h e a b s e n c e o f sy nc in p u t. a 32- s t ep s a m p ling c l o c k p h a s e a d j u s t m e n t i s p r o v i d e d . o u t p u t d a t a , s y n c , a n d clo c k phas e r e la t i o n sh i p s a r e m a in t a i n e d . t h e au t o - o f f s e t f e at u r e c a n b e e n a b l e d t o au t o m a t i c a l l y r e s t o r e t h e sig n al r e fer e n c e l e v e l s and to a u t o ma t i cal l y calib r a t e o u t an y o f fs et dif f er en ces betw een t h e t h r e e c h a n n e ls. the ad9980 als o o f fers f u l l syn c p r o c es sin g fo r co m p osi t e sy n c and sy n c -on- g r e e n a p pli c a t ion s . a clam p sig n a l is gen e r a t e d in t e r n a l ly o r m a y b e p r o v i d e d b y th e use r thr o ugh th e clamp i n p u t p i n . f a b r ica t ed in an ad van c e d cmos p r o c es s, the ad9980 is p r o v ide d i n a sp ace-s a v i ng, 80-pin, pb-f r e e, lqfp sur f ace m o u n t pl ast i c p a cka g e . i t is sp e c if ie d o v er t h e 0 c t o +70c t e m p era t ur e ra ng e .
ad9980 rev. 0 | page 2 of 44 table of contents analog interface specifications ....................................................... 3 electrical characteristics ............................................................. 3 absolute maximum ratings ............................................................ 5 explanation of test levels ........................................................... 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 design guide ................................................................................... 10 general description ................................................................... 10 digital inputs .............................................................................. 10 input signal handling ................................................................ 10 hsync and vsync inputs ............................................................ 10 serial control port ..................................................................... 10 output signal handling ............................................................. 10 clamping ..................................................................................... 10 gain and offset control ............................................................ 11 timing diagrams ........................................................................ 19 hsync timing ............................................................................. 20 coast timing ............................................................................... 20 output formatter ....................................................................... 20 two-wire serial register map ...................................................... 22 detailed 2-wire serial control register descriptions .............. 28 chip identification ..................................................................... 28 pll divider control .................................................................. 28 clock generator control .......................................................... 28 phase adjust ................................................................................ 29 input gain ................................................................................... 29 input offset ................................................................................. 29 hsync controls ........................................................................... 29 vsync controls ........................................................................... 30 coast and clamp controls ........................................................ 31 sog control ............................................................................... 33 input and power control ........................................................... 33 output control ........................................................................... 34 sync processing .......................................................................... 35 detection status .......................................................................... 36 polarity status ............................................................................. 36 hsync count ............................................................................... 37 two-wire serial control port ....................................................... 38 data transfer via serial interface ............................................. 38 pcb layout recommendations ............................................... 40 pll ............................................................................................... 40 outline dimensions ....................................................................... 42 ordering guide .......................................................................... 42 revision history 1/05initial version: revision 0
ad9980 rev. 0 | page 3 of 44 analog interface specifications electrical characteristics v d = 3.3 v, v dd = 3.3 v, pv d = 1.8 v, dav dd = 1.8 v, adc clock = maximum conversion rate, full temperature range = 0c to 70c. table 1. AD9980KSTZ-80 1 ad9980kstz-95 2 parameter temp test level min typ max min typ max unit resolution number of bits 8 8 bits lsb size 0.39 0.39 % of full scale dc accuracy lsb differential nonlinearity 80 msps conversion rate 25c full i vi 0.2 0.2 0.75 1.0 0.2 0.2 0.75 1.0 lsb differential nonlinearity 95 msps conversion rate 25c full i vi 0.6 0.75 1.5 2.25 lsb integral nonlinearity 80 msps conversion rate 25c full i vi 0.3 0.3 1.0 1.3 0.3 0.3 1.0 1.3 lsb integral nonlinearity 95 msps conversion rate 25c full i vi 0.6 0.9 2.25 3.2 lsb no missing codes 25c i guaranteed guaranteed analog input input voltage range minimum full vi 0.5 0.5 v p-p maximum full vi 1.0 1.0 v p-p gain tempco 25c v 105 105 ppm/c input bias current 25c v 1 1 a full v 1 1 a input full-scale matching full vi 1 9 1 10 % fs offset adjustment range full vi 44 44 % fs switching performance maximum conversion rate full vi 80 95 msps minimum conversion rate full iv 10 10 msps data to clock skew t skew full iv ?0.5 +2 ?0.5 +2 ns t buff full vi 4.7 4.7 s t stah full vi 4.0 4.0 s t dho full vi 0 0 s t dal full vi 4.7 4.7 s t dah full vi 4.0 4.0 s t dsu full vi 250 250 ns t stasu full vi 4.7 4.7 s t stosu full vi 4.0 4.0 s maximum pll clock rate full vi 80 95 mhz minimum pll clock rate full iv 10 10 mhz pll jitter 25c iv 750 980 ps p-p full iv ps p-p sampling phase tempco full iv 15 15 ps/c digital inputs 3 input voltage, high (v ih ) full vi 2.5 2.5 v input voltage, low (v il ) full vi 0.8 0.8 v input current, high (i ih ) full v C82 C82 a input current, low (i il ) full v 82 82 a input capacitance 25c v 2 2 pf
ad9980 rev. 0 | page 4 of 44 AD9980KSTZ-80 1 ad9980kstz-95 2 parameter temp test level min typ max min typ max unit digital outputs output voltage, high (v oh ) full vi v dd ? 0.2 v dd ? 0.1 v output voltage, low (v ol ) full vi 0.2 0.1 v duty cycle, datack full iv 50 50 % output coding binary binary power supply v d supply voltage full iv 3.13 3.3 3.47 3.13 3.3 3.47 v v dd supply voltage full iv 1.7 3.3 3.47 1.7 3.3 3.47 v pv d supply voltage full iv 1.7 1.8 1.9 1.7 1.8 1.9 v dav d supply voltage full iv 1.7 1.8 1.9 1.7 1.8 1.9 v i d supply current (v d ) 25c v 233 240 ma i dd supply current (v dd ) 4 25c v 42 49 ma ip vd supply current (p vd ) 25c v 11 8 ma idav d supply current (dav d ) 25c v 10 12 ma total power dissipation full vi 953 1070 993 1114 mw power-down supply current full vi 18 27 18 28 ma power-down dissipation full vi 55 81 55 88 mw dynamic performance analog bandwidth, full power 25c v 200 200 mhz crosstalk full v 60 60 dbc thermal characteristics jc , junction-to-case thermal resistance v 16 16 c/w ja , junction-to-ambient thermal resistance v 35 35 c/w 1 output drive strength = 0 was used for all 80 mhz parameters. 2 output drive strength = 1 was used for all 95 mhz parameters. 3 digital inputs are hsync0, hsync1, vsync0, vsync1, sda, scl, extclk, clamp, and pwrdn. 4 datack load = 10 pf, data load = 5 pf.
ad9980 rev. 0 | page 5 of 4 4 absolute maximum ratings table 2. p a r a m e t e r r a t i n g v d 3.6 v v dd 3.6 v pv d 1.98 v dav dd 1.98 v analog inputs v d to 0.0 v r e f h i v d to 0.0 v r e f c m v d to 0.0 v r e f l o v d to 0.0 v digital inputs 5 v to 0.0 v digital output c u rrent 20 ma functional temperature ?25c to + 85c storage temperature ?65c to + 150c maximum junction temperature 150c s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y a nd f u n c t i o n al op era t io n o f t h e de v i ce a t t h es e o r an y ot he r c o nd it i o ns out s i d e of t h o s e i n d i c a te d i n t h e op e r a t i o n s e c t io n s o f t h is sp e c if ic a t ion is n o t i m plie d . e x p o sur e t o a b so l u t e maxim u m ra tin g s f o r ext e n d ed p e r i o d s ma y a f f e ct de vice r e l i ab i l i t y . explanation of test levels test level i. 100% p r o d uc tion t e st ed . ii. 100% p r o d uc tion t e st ed a t 25c a nd s a m p le t e sted a t sp e c if ie d t e m p e r a t ur es. iii. s a m p l e te ste d on ly . iv. p a r a me te r i s g u ar an te e d b y d e s i g n a n d ch ar a c te r i z a t i on te st i n g . v. p a ra m e t e r is a typ i cal val u e o n ly . vi. 100% p r o d uc tion t e st ed a t 25c; gua r a n t e ed b y desig n and ch ar a c te r i z a t i on te st i n g . esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad9980 rev. 0 | page 6 of 4 4 pin conf iguration and fu nction descriptions 04740-001 2 b ain0 3 gnd 4 b ain1 7 gnd 6 g ain0 5 v d (3.3v) 1 v d (3.3v) 8 sogin0 9 v d (3.3v) 10 g ain1 12 sogin1 13 v d (3.3v) 14 r ain0 15 gnd 16 r ain1 17 pwrdn 18 reflo 19 refcm 20 refhi 11 gnd 59 58 57 54 55 56 60 53 52 blue <2> blue <3> blue <4> blue <7> blue <6> blue <5> blue <1> gnd v dd (3.3v) 51 nc 49 green <0> 48 green <1> 47 green <2> 46 green <3> 45 green <4> 44 green <5> 43 green <6> 42 green <7> 41 dav dd (1.8) 50 nc nc = no connect 21 o/e field 22 vsou t /a 0 23 hs out 24 sogout 25 datack 26 v dd ( 3 .3v) 27 gnd 28 re d <7 > 29 re d <6 > 30 re d <5 > 31 re d <4 > 32 re d <3 > 33 re d <2 > 34 re d <1 > 35 re d <0 > 36 nc 37 nc 38 v dd ( 3 .3v) 39 gnd 40 gnd 80 gnd 79 pv d ( 1 .8v) 78 filt 77 gnd 76 pv d ( 1 .8v) 75 gnd 74 pv d ( 1 .8v) 73 clamp 72 e x t clk/coas t 71 vsyn c 0 70 hs y nc0 69 vsyn c 1 68 hs y nc1 67 sc l 66 sd a 65 gnd 64 v dd ( 3 .3v) 63 nc 62 nc 61 blue <0 > pin 1 ad9980 top view (not to scale) f i gure 2. t o p view ( p in d o wn) table 3. co mpl e te pinout list pin type mnemonic function value pin no. i n p u t s r ain 0 channe l 0 analog input for converter r 0.0 v to 1.0 v 14 r ain 1 channe l 1 analog input for converter r 0.0 v to 1.0 v 16 g ain 0 channe l 0 analog input for converter g 0.0 v to 1.0 v 6 g ain 1 channe l 1 analog input for converter g 0.0 v to 1.0 v 10 b ain 0 channe l 0 analog input for converter b 0.0 v to 1.0 v 2 b ain 1 channe l 1 analog input for converter b 0.0 v to 1.0 v 4 hsync0 horizontal sync input for channel 0 3.3 v cmos 70 hsync1 horizontal sync input for channel 1 3.3 v cmos 68 vsync0 vertical sync input for channel 0 3.3 v cmos 71 vsync1 vertical sync input for channel 1 3.3 v cmos 69 sogin0 input for sync-on-green channel 0 0.0 v to 1.0 v 8 sogin1 input for sync-on-green channel 1 0.0 v to 1.0 v 12 ext c k external cl ock i n put 3.3 v cmos 72 1 clamp external clamp i n put signal 3.3 v cmos 73 coast external pll coast si gnal input 3.3 v cmos 72 1 pwrdn power-down control 3.3 v cmos 17 o u t p u t s r e d [7:0 ] outputs of converter r, bit 7 is the msb 3.3 v cmos 28C35 green [7:0] outputs of converter g, bit 7 is the msb 3.3 v cmos 42C49 blue [7:0] outputs of converter b, bit 7 is the msb 3.3 v cmos 54C61 datack data output clock 3.3 v cmos 25
ad9980 rev. 0 | page 7 of 44 pin type mnemonic function value pin no. hsout hsync output clock (phase-ali gned with datack) 3.3 v cmos 23 vsout vsync output clock 3.3 v cmos 22 2 sogout sync-on-green slicer output 3.3 v cmos 24 o/e field odd/even fi eld output 3.3 v cmos 21 references filt connection for external filter components for internal pll 78 reflo connection for external ca pacitor for input amplifier 18 refcm connection for external capacitor for input amplifier 19 refhi connection for external ca pacitor for input amplifier 20 power supply v d analog power supply 3.3 v 1, 5, 9, 13 v dd output power supply 1.8 v or 3.3 v 26, 38, 52, 64 pv d pll power supply 1.8 v 74, 76, 79 dav dd digital logic power supply 1.8 v 41 gnd ground 0 v 3, 7, 11, 15, 27, 39, 40, 53, 65, 75, 77, 80 control sda serial port data i/o 3.3 v cmos 66 scl serial port data clock (100 khz maximum) 3.3 v cmos 67 a0 serial port address input 3.3 v cmos 22 2 1 extclk and coast share the same pin. 2 vsout and a0 share the same pin.
ad9980 rev. 0 | page 8 of 44 table 4. pin function descriptions pin description inputs rain0 analog input for the red channel 0. gain0 analog input for the green channel 0. bain0 analog input for the blue channel 0. rain1 analog input for the red channel 1. gain1 analog input for the green channel 1. bain1 analog input for the blue channel 1. high impedance inputs that accept the red, green, and blue channel graphics signals, respectively. the three channels are id entical and can be used for any colors, but colors are assigned for convenient reference. they accommodate inp ut signals ranging from 0.5 v to 1.0 v full scale. signals should be ac-coupled to these pins to support clamp operation. hsync0 horizontal sync input channel 0. hsync1 horizontal sync input channel 1. th ese inputs receive a logic signal th at establishes the horizontal timing reference and provides the frequency reference for pixel clock generation. the logic sense of this pin can be automatically determined by the chip or manually controlled by serial regist er 0x12, bits [5:4] (hsync polarity). only the leading edge of hsync is used by the pll; the trailing edge is used in clamp timing. when hsync polarity = 0, the falling edge of hsync is used. when hsync polarity = 1, the rising edge is active. the input includes a schmitt trigger for noise immunity. vsync0 vertical sync input channel 0. vsync1 vertical sync input channel 1. these are the inputs for vertical sync and provide timing information for generation of the field (odd/even) and in ternal coast generation. the logic sense of this pin can be automatically determined by the chip or manually controlled by serial register 0x14, bits [5:4] (vsync polarity). sogin0 sync-on-green input channel 0. sogin1 sync-on-green input channel 1. these inputs are provid ed to assist with processing signals with embedded sync, typically on the green channel. the pin is connect ed to a high speed comparator with an internally generated threshold. the threshold level can be progra mmed in 8 mv steps to any voltage between 8 mv and 256 mv above the negative peak of the input signal. th e default voltage threshold is 128 mv. when connected to an ac-coupled graphics signal with embedded sync, it produces a noninverting digital output on sogout. (this is usually a composite sync sign al, containing both vertical and horizont al sync information that must be separated before passing the horizontal sync signal for hsync processing.) when not used, this input should be left unconnected. for more details on this function and how it should be config ured, refer to the sync-on- green section. clamp external clamp input (optional). this lo gic input may be used to define the t ime during which the input signal is clamped to ground or midscale. it should be exercised when the reference dc level is known to be present on the analog input channels, typically du ring the back porch of the graphics signal. the clamp pin is enabled by setting the control bit clamp function to 1, (register 0x18, bit 4; default is 0). when di sabled, this pin is ignored and the clamp timing is determined inte rnally by counting a delay and durati on from the trailing edge of the hsync input. the logic sense of this pin can be automatically determined by the chip or controlled by clamp polarity register 0x1b, bits [7:6]. when not used, this pin may be left unconne cted (there is an internal pull-down resistor) and the clamp function programmed to 0. extclk/coast coast input to clock generator (optio nal). this input may be used to ca use the pixel clock generator to stop synchronizing with hsync and continue producing a clock at its current frequency and ph ase. this is useful when processing signals from sources that fa il to produce hsync pulses during the vertical interval. the coast signal is generally not required for pc-generated signals. the logic sens e of this pin can be determined automatically or controlled by coast polarity (register 0x18, bits [7:6]). when not used and extclk is not used, this pin may be grounded and coast polarity programmed to 1. input coast polarity defaults to1 at power-up. this pin is shared with the extclk function, which does not affect coast functionality. fo r more details on extclk, see the description in this section. extclk/coast external clock. this allows the insert ion of an external clock source rath er than the internally generated, pll locked clock. extclk is enabled by programming register 0x03, bit 2 to 1. this pin is shared with the coast function, which does not affect extclk functionality. for more details on coast, see the description in this section. pwrdn power-down control. this pin can be used along with re gister 0x1e, bit 3 for manu al power-down control. if manual power-down control is selected (register 0x1e, bit 4) and this pin is not used , it is recommended to set the pin polarity (register 0x1e, bit 2) to active high an d hardwire this pin to ground with a 10 k? resistor. reflo refcm refhi input amplifier reference. reflo and refhi are connected together through a 10 f capacitor; refcm is connected through a 10 f capacitor to ground. these ar e used for stability in th e input pga (programmable gain amplifier) circuitry. see figure 5.
ad9980 rev. 0 | page 9 of 44 pin description filt external filter connection. for proper operation, the pixel clock generator pll requires an external filter. connect the filter shown in figure 7 to this pin. for optimal performance, minimize noise and parasitics on this node. for more information see the pcb layout recommendations section. outputs hsout horizontal sync output. a reconstruc ted and phase-aligned version of the hsync input. both the polarity and duration of this output can be programmed via serial bu s registers. by maintaining alignment with datack and data outputs, data timing with respect to hsync can always be determined. vsout/a0 vertical sync output. pin shared with a0, serial port address. this can be either a separated vsync from a composite signal or a direct pass through of the vsync signal. the polarity of this output can be controlled via a serial bus bit. the placement and duration in all modes can be set by the graphics transmitter or the duration can be set by register 0x14 and register 0x15. this pin is shared with the a0 func tion, which does not affect vsync output functionality. for more details on a0, see the description in the serial control port section. sogout sync-on-green slicer output. this pi n outputs one of four possible sign als (controlled by register 0x1d, bits [1:0]): raw sog, raw hsync, regenerated hsync from the filter, or the filt ered hsync. see the sync processing block diagram (figure 8) to view how this pin is connected. (besides slicing off sog, the output from this pin gets no other additional processing on the ad9980. vsync separation is performed via the sync separator.) o/e field odd/even field bit for interlaced video. this output will identify whether the current fi eld (in an interlaced signal) is odd or even. serial port sda serial port data i/o. scl serial port data clock. vsout/a0 serial port address input 0. pin shared with vsout. this pin selects the lsb of the serial port device address, allowing two analog devices parts to be on the same se rial bus. a high impedance external pull-up resistor enables this pin to be read at power-up as 1, or a high impedance, external pull-down resistor enables this pin to be read at power-up as a 0 and not interfere with the vs out functionality. for more details on vsout, see the outputs section in this table. data outputs red [7:0] data output, red channel. green [7:0] data output, green channel. blue [7:0] data output, blue channel. the main data outputs. bit 7 is the msb. the delay from pixel sampling time to output is fixed. when the sampling time is changed by adjusting the phase register, the output t iming is shifted as well. the datack and hsout outputs are also moved, so the timing relationship among the signals is maintained. data clock output datack data clock output. this is the main clock output signal used to strobe the output data and hsout into external logic. four possible output clocks can be selected with register 0x20, bits [7:6]. three of these are related to the pixel clock (pixel clock, 90 phase-shifted pixel clock, an d 2 frequency pixel clock). th ey are produced either by the internal pll clock generator or extclk and are synchr onous with the pixel sampling clock. the fourth option for the data clock output is an in ternally generated 40 mhz clock. the sampling time of the internal pixel clock can be changed by adjusting the phase register (register 0x04). when this is changed, the pixel related datack timing is also shifted. the data , datack, and hsout outputs are all moved so that the timing relation ship among the signals is maintained. power supply v d (3.3 v) main power supply. these pins supply power to the main el ements of the circuit. they should be as quiet and filtered as possible. v dd (1.8 v to 3.3 v) digital output power supply. a large nu mber of output pins (up to 29) switching at high speed (up to 95 mhz) generate a lot of power supply transients (noise). th ese supply pins are identified separately from the v d pins, so special care can be taken to minimize output noise transfe rred into the sensitive analog circuitry. if the ad9980 is interfacing with lower voltage logic, v dd may be connected to a lower supply voltage (as low as 1.8 v) for compatibility. pv d (1.8 v) clock generator power supply. the most sensitive portion of the ad9980 is the clock generation circuitry. these pins provide power to the clock pll an d help the user design for optimal performance. the designer should provide quiet, noise-free power to these pins. dav dd (1.8 v) digital input power supply. th is supplies power to the digital logic. gnd ground. the ground return for all circuitry on-chip. it is recommended that the ad9980 be assembled on a single solid ground plane, with careful attention to ground current paths.
ad9980 rev. 0 | page 10 of 44 design guide general description the ad9980 is a f u l l y in t e g r a t e d s o l u tion f o r ca p t ur in g a n alog rgb o r ypbpr sig n a l s a nd dig i t i zin g t h e m fo r displa y on ad van c e d t v s, f l a t p a nel m o n i to rs, p r o j e c to rs, a nd o t h e r ty p e s o f dig i t a l di spl a y s . i m plem e n te d in a hig h - p er fo r m a n ce cmo s p r o c es s, t h e in te r f ace ca n ca pt ure sig n als w i t h pi xe l ra t e s o f u p t o 95 mh z. the ad9980 inc l udes al l n e cess a r y in p u t b u f f er in g, sig n al dc r e sto r a t io n (clam p ing), o f fs et a nd ga in ( b r i g h t n ess a nd con t r a st) ad j u st m e n t , p i xel clo c k ge n e r a t i o n , s a m p li n g ph as e con t r o l, a n d o u t p u t da t a f o r m a t ting. al l co n t r o ls a r e p r ogra mma b l e v i a a t w o - w i r e se rial in t e rf a c e ( i 2 c ? ). f u l l in t e g r a t ion o f t h es e s e n s i t i v e a n alog f u n c tio n s ma k e s sys t em des i g n s t ra ig h t fo r w a r d a nd less s e n s i t i v e to t h e ph y s ica l a nd ele c t r ica l e n vir o n m e n t. w i t h a ty p i c a l p o w e r dissi p a t ion o f less t h a n 90 0 mw a nd an o p era t i n g t e m p era t ur e ra n g e o f 0c t o 70c, t h e de vic e r e q u ir e s n o s p eci a l en vi r o n m en tal co n s id e r a t i o n s . digi tal in p u ts al l dig i tal in p u ts o n the ad998 0 o p era t e t o 3.3 v cm os lev e l s. the fol l o w in g dig i t a l i n p u ts a r e 5 v t o lera n t (a ppl yin g 5 v t o t h e m do es n o t c a us e an y da ma ge): hs ync0, h s ync1, v s y n c 0 , v s y n c 1 , s o g i n 0 , s o g i n 1 , s d a , s c l a n d c l a m p . inpu t sig n al handli ng the ad9980 has six hig h -im p e d an c e a n alog in p u t p i ns f o r th e r e d , g r e e n, an d b l ue cha n nels. t h e y acco m m o d a t e sig n a l s ra n g in g f r o m 0. 5 v t o 1.0 v p-p . sig n a l s a r e typ i c a l l y b r o u g h t o n to t h e i n t e r f ace b o a r d wi t h a d v i-i co nn ec t o r , a 15-p i n d conn ec t o r , o r r c a co nn ec t o rs. the ad9980 sho u ld be lo ca t e d as c l os e as p o s s ib le t o the in p u t co nne c t o r . sig n a l s sh o u ld b e r o u t e d usin g m a tch e d-i m p e dan c e tra c e s (n o r m a ll y 75 ?) t o th e i c i n p u t p i n s . a t th e in p u t p i ns th e sig n al sh ou ld be r e sis t i v e l y t e r m ina t e d (75 ? t o th e sig n al g r o u n d r e t u r n ) a n d c a p a ci tiv e l y co u p led t o th e ad9980 in p u ts thr o ug h 47 nf ca p a c i t o rs. th es e ca p a c i t o rs f o r m p a r t o f th e dc r e s t o r a t ion c i r c ui t. i n an ide a l w o rl d o f p e r f e c t l y m a tch e d i m p e dances, t h e b e st pe rf o r m a n c e c a n be o b ta i n ed w i t h th e w i d e s t po s s i b l e s i gn a l ba ndwid th. th e wide ban d wid t h in p u ts o f the ad9980 (200 mh z) can co n t in uo us l y trac k t h e in p u t sig n al as i t m o v e s f r o m o n e pixel le vel to t h e n e x t a nd can d i g i t i z e t h e pixel d u r i ng a lo n g , f l a t p i xe l t i me . i n man y sys t em s, h o we v e r , t h er e a r e mis- ma t c h e s, r e f l e c t i o n s, a nd n o is e , w h ich can r e su lt in excessi v e r i ng i n g a n d d i st or t i on of t h e i n put w a ve f o r m . t h i s m a ke s it m o r e dif f i c u l t t o es t a b l is h a s a m p lin g phas e t h a t p r o v ides g o o d ima g e q u al i t y . i t has be en sh own tha t a smal l ind u c t o r in s e r i es w i t h t h e in p u t is e f f e cti v e i n r o lli n g o f f th e in p u t ba n d w i d t h slig h t ly an d p r ovid in g a hig h qua l i t y sig n a l o v er a wid e r ra n g e o f co n d i t io n s . u s in g a f a ir -r i t e #2508051217z0 hig h sp ee d , sig n a l chi p b e a d ind u c t o r in t h e cir c ui t sh o w n in f i gur e 3 g i v e s go o d re su l t s i n mo st a p pl ic a t ions . rgb input r ain g ain b ain 47nf 75 ? 04740-002 f i gure 3. a n alog in put inter f ac e cir c u i t hsync and vsync inpu ts the i n t e r f ace al s o accep t s h s y n c a nd v e r t ical sy n c p e r i o d (vsy n c ) sig n als, whic h a r e us e d t o g e n e r a t e t h e p i xe l c l o c k, cla m p t i mi n g , c o ast an d f i el d in fo r m a t io n. t h es e can b e ei t h er a sy n c sig n al dir e c t l y f r o m th e g r a p hics s o ur ce , o r a pre p ro c e ss e d t t l or c m o s l e vel s i g n a l . the h s y n c i n p u t in cl udes a s c hmi t t t r ig g e r b u f f er fo r imm u ni ty t o n o is e an d sig n als wi t h lo n g r i s e tim e s. i n typ i cal pc-bas e d g r a p hic sys t ems , th e sy n c sig n al s a r e sim p l y t t l - le ve l dr i v ers f eed i n g un s h ie l d ed w i r e s in t h e m o ni t o r ca b l e . a s s u ch , n o t e r m ina t ion is re q u ir e d . serial control port the s e r i al con t rol p o r t is desig n ed f o r 3.3 v log i c; h o w e v e r , i t is t o lera n t o f 5 v log i c sig n als. o u t p ut s i gn a l h a n d li n g the dig i t a l o u t p u t s a r e desig n e d t o o p era t e f r o m 1.8 v t o 3.3 v (v dd ). clamping rgb cla m ping t o p r o p e r l y d i g i ti ze th e in co min g si gn al , th e d c o f fse t o f th e in p u t m u s t b e ad j u s t e d t o f i t t h e ra n g e o f t h e on- b o a r d ad cs. m o s t g r a p hics s y s t em s p r o d uc e r g b sig n als wi t h b l ac k a t g r o u n d and w h i t e a t a p p r o x ima t e l y 0.75 v . h o w e v e r , if syn c sig n als a r e em b e dde d in t h e g r a p hics, t h e sy n c t i p is o f t e n a t g r o u n d and blac k is a t 300 mv . then whi t e is a t a p p r o x ima t e l y 1.0 v . s o m e comm on r g b l i ne a m p l if ier bo xes us e emi t t e r - fol l o w er b u f f ers t o s p li t sig n als a nd i n cr e a s e dr iv e ca p a b i l i ty . this in tr o d uces a 700 mv dc o f fs et t o th e sig n a l , whic h m u s t b e r e m o v e d f o r p r o p er ca p t ur e b y th e ad9980. the k e y t o cl a m p i n g is t o ide n t i f y a p o r t io n (t im e) o f t h e sig n a l w h en t h e g r a p hic sys t em is k n ow n t o b e p r o d u c in g b l ack. a n o f fse t i s th e n in t r od uced tha t r e s u l t s in th e ad c s p r od uci n g a b l ack o u t p u t (c o d e 0x00) w h en t h e k n o w n black in p u t is p r es en t. the o f fs et t h en r e mains in place w h e n o t h e r sig n al le v e l s a r e p r o c ess e d , and t h e en t i r e sig n al is s h if t e d t o e l imi n a t e o f fs et er r o rs.
ad9980 rev. 0 | page 11 of 44 in most pc graphics systems, black is transmitted between active video lines. with crt displays, when the electron beam has completed writing a horizontal line on the screen (at the right side), the beam is deflected quickly to the left side of the screen (called horizontal retrace) and a black signal is provided to prevent the beam from disturbing the image. in systems with embedded sync, a blacker-than-black signal (hsync) is produced briefly to signal the crt that it is time to begin a retrace. because the input is not at black level at this time, it is important to avoid clamping during hsync. fortunately, there is virtually always a period following hsync, called the back porch, where a good black reference is provided. this is the time when clamping should be done. the clamp timing can be established by simply exercising the clamp pin at the appropriate time with clamp source (register 0x18, bit 4) = 1. the polarity of this signal is set by the clamp polarity bit (register 0x1b, bits [7:6]). a simpler method of clamp timing uses the ad9980s internal clamp timing generator. the clamp placement register (register 0x19) is programmed with the number of pixel periods that should pass after the trailing edge of hsync before clamping starts. a second register, clamp duration, (register 0x1a) sets the duration of the clamp. these are both 8-bit values, providing considerable flexibility in clamp generation. the clamp timing is referenced to the trailing edge of hsync because, though hsync duration can vary widely, the back porch (black reference) always follows hsync. a good starting point for establishing clamping is to set the clamp placement to 0x04 (providing 4 pixel periods for the graphics signal to stabilize after sync) and set the clamp duration to 0x28 (giving the clamp 40 pixel periods to reestablish the black reference). clamping is accomplished by placing an appropriate charge on the external input coupling capacitor. the value of this capacitor affects the performance of the clamp. if it is too small, there will be a significant amplitude change during a horizontal line time (between clamping intervals). if the capacitor is too large, then it will take excessively long for the clamp to recover from a large change in incoming signal offset. the recommended value (47 nf) results in recovering from a step error of 100 mv to within ? lsb in 20 lines with a clamp duration of 20 pixel periods on a 85 hz xga signal. ypbpr clamping ypbpr graphic signals are slightly different from rgb signals in that the dc reference level (black level in rgb signals) for the color difference signals is at the midpoint of the video signal rather than at the bottom. the three inputs are composed of luminance (y) and color difference (pb and pr) signals. for the color difference signals it is necessary to clamp to the midscale range of the adc range (128) rather than at the bottom of the adc range (0) while the y channel is clamped to ground. clamping to midscale rather than ground can be accomplished by setting the clamp select bits in the serial bus register. each of the three converters has its own selection bit so that they can be independently clamped to either midscale or ground. these bits are located in register 0x18, bits [3:1]. the midscale reference voltage is internally generated for each converter. gain and offset control the ad9980 contains three pgas, one for each of the three analog inputs. the range of the pga is sufficient to accom- modate input signals with inputs ranging from 0.5 v to 1.0 v full scale. the gain is set in three 7-bit registers (red gain [0x05], green gain [0x07], blue gain [0x09]). for each register, a gain setting of 0 corresponds to the highest gain, while a gain setting of 127 corresponds to the lowest gain. note that increasing the gain setting results in an image with less contrast. the offset control shifts the analog input, resulting in a change in brightness. three 9-bit registers (red offset [0x0b, 0x0c], green offset [0x0d, 0x0e], blue offset [0x0f, 0x10]) provide independent settings for each channel. the function of the offset register depends on whether auto-offset is enabled (register 0x1b, bit 5). if manual offset is used, seven bits of the offset registers (for the red channel register 0x0b, bits [6:0] control the absolute offset added to the channel. the offset control provides 63 lsbs of adjustment range, with one lsb of offset corresponding to one lsb of output code. automatic offset in addition to the manual offset adjustment mode, the ad9980 also includes circuitry to automatically calibrate the offset for each channel. by monitoring the output of each adc during the back porch of the input signals, the ad9980 can self-adjust to eliminate any offset errors in its own adc channels and any offset errors present on the incoming graphics or video signals. to activate the auto-offset mode, set register 0x1b, bit 5 to 1. next, the target code registers (0x0b through 0x10) must be programmed. the values programmed into the target code registers should be the output code desired from the ad9980 adcs, which are generated during the back porch reference time. for example, for rgb signals, all three registers are normally programmed to code 1, while for ypbpr signals the green (y) channel is normally programmed to code 1 and the blue and red channels (pb and pr) are normally set to 128. the target code registers have nine bits per channel and are in twos complement format. this allows any value between C256 and +255 to be programmed. although any value in this range can be programmed, the ad9980s offset range may not be able to reach every value. intended target code values range from (but are not limited to) C40 to C1 and +1 to +40 when ground clamping and +88 to +168 when midscale clamping. (note that a target code of 0 is not valid.)
ad9980 rev. 0 | page 12 of 44 n e g a t i v e t a rg et co des a r e i n cl ude d i n o r der t o d u plica t e a fe a- t u r e t h a t is p r es en t wi t h man u a l o f fs et ad j u s t men t . the b e nef i t t h a t is b e ing mi mick e d is t h e ab i l i t y t o e a si ly a d j u st b r ig h t n e ss o n a dis p l a y . b y s e t t in g t h e ta rg et co de t o a val u e tha t do es n o t co r r es p o n d t o t h e i d e a l a d c ran g e , t h e e nd r e su l t is a n ima g e t h a t is e i t h er b r i g h t er o r da rk er . a t a rg et co de hi g h er t h an ide a l r e su l t s in a b r ig h t er im a g e w h i l e a t a rget co de l o w e r t h a n ide a l r e su l t s in a d a rk er ima g e . the a b i l i t y t o p r og ra m a t a rg et c o de g i v e s a la rg e deg r e e o f f r eed o m a n d f l exi b ili t y . w h ile in m o s t case s all c h a n n e ls w i ll be s e t t o ei t h er 1 o r 128, th e f l exi b il i t y t o s e lec t o t h e r val u es a l lo ws fo r t h e p o ssi b i l i t y o f in s e r t in g in t e n t io na l sk e w s b e tw e e n c h a n n e ls. i t als o al lo ws th e ad c ra n g e t o be sk ew e d s o tha t v o l t a g es o u tside o f t h e n o r m al ra n g e can b e dig i t i ze d . f o r e x a m p l e , se t t i n g th e ta r g e t cod e t o 40 allo w s th e syn c t i p , w h i c h is n o r m a l ly b e low b l ack le vel, t o b e d i g i t i z e d and e v a l u a t e d . the i n t e r n al log i c fo r t h e a u t o -of f s e t cir c ui t r e q u ir es 16 da t a clo c k c y cles t o p e r f o r m i t s f u nc t i o n . this op era t io n is exe c u t e d imm e di a t e l y a f ter t h e clam pin g p u ls e . th er efo r e, i t is im p o r t a n t t o end t h e clam p i n g p u ls e sig n a l a t le ast 16 d a t a clo c k c y cles bef o r e ac ti v e video . this is tr ue whether usin g th e ad9980 s i n te r n a l cl am p c i rc u i t or an e x te r n a l cl am p s i g n a l . t h e a u to - of f s e t f u nc t i on c a n b e pro g r a m m e d to r u n c o n t i n u o u sly or on a o n e-tim e b a sis (s ee a u t o -o f f s e t h o ld , reg i s t er 0x2c, b i t 4). i n co n t in uo us m o de , th e u p da t e f r eq uen c y c a n be p r og ra mm e d (reg ist e r 0x1b , bi ts [ 4 :3] ) . c o n t in uo us o p era t ion w i t h u p d a t e s ev er y 64 h s yn c s is r e co mmen d ed . a guide l i n e fo r b a sic a u t o -o f f s e t o p era t ion is sho w n i n t a b l e 5 a nd t a b l e 6. table 5. r g b auto-offset re gister settings regist e r v a l u e c o mmen t s 0x0b 0x02 s e ts r e d tar g et t o 4 0x0c 0x00 must be wr itten 0x0d 0x02 s e ts g r een tar g et to 4 0x0e 0x00 must be wr itten 0x0f 0x02 s e ts blue tar g et to 4 0x10 0x00 must be wr itten 0x18, bits [3:1] 000 s e ts r e d , g r een, and blue channe ls to gr o u nd clamp 0x1b , bit [5:3] 110 s e lec t s upda te ra te and enabl e s auto - o ffset. table 6. pbpr auto-offset re gister settings regist e r v a l u e c o mmen t s 0x0b 0x40 s e ts p r (r ed) tar g et to 128 0x0c 0x00 must be wr itten 0x0d 0x02 s e ts y (g r een) tar g et to 4 0x0e 0x00 must be wr itten 0x0f 0x40 s e ts p b (blue) ta r g et to 128 0x10 0x00 must be wr itten 0x18 bits [3:1] 101 s e ts p b , p r to midscale clamp and y to gr ound clamp 0x1b , bit [5:3] 110 s e lec t s upda te ra te and enabl e s auto - o ffset sync - o n- r een the sy n c -on-g r e e n i n p u t op era t es in tw o s t eps. f i rs t, i t s e ts a b a s e l i n e cl a m p l e vel of f of t h e i n c o m i ng v i d e o s i g n a l w i t h a n e g a ti ve p e a k det e c t o r . s e cond , i t s e ts t h e sy n c t r ig g e r lev e l t o a p r og ra mma b l e (reg ist e r 0x1d , bi ts [7:3]) le v e l (typ ic al l y 128 mv) abo v e th e n e g a ti ve p e a k . th e sy n c -o n-g r een in p u t m u s t be a c -co u p l ed t o th e gr een a n al og i n p u t t h r o ugh i t s o w n ca p a c i t o r . th e val u e o f th e c a p a ci t o r m u s t be 1 nf 20%. i f sy n c -o n - g r e e n i s n o t us e d , t h is co nne c t io n is no t r e q u ir e d . t h e s y n c - o n- gr ee n si gn al al w a ys h a s n e ga ti v e po l a ri ty . r ain b ain g ain sog 47nf 47nf 47nf 1nf 04740-003 f i gure 4. t y pic a l in put c o nfigu r ation reference bypa ssing ref l o an d ref h i a r e co nne c t e d to e a ch o t h e r t h r o ug h a 1 0 f c a p a c i tor . r e f c m i s c o n n e c te d to g r ou nd t h rou g h a 10 f ca pa ci t o r . t h ese r e f e r e n c es a r e used b y th e i n p u t pga cir c ui tr y . refhi reflo refcm 10 f 10 f 04740-014 f i gure 5. input a m plifi e r r e f e renc e ca pac i to rs clock eneration a p l l i s em p l o y ed t o g e n e ra t e th e p i x e l c l oc k . t h e h s yn c in p u t p r o v ides a r e fer e n c e f r e q uen c y t o t h e pll. a v o l t a g e con t r o l l e d osc i ll a t o r (v co) g e n e ra t e s a m u c h h i g h e r p i x e l c l oc k f r e q uen c y . this p i xel clo c k is d i vide d b y t h e pl l divide v a l u e (reg ist e r 0x01 a nd reg i s t er 0x0 2 ) a nd p h as e-com p a r ed wi th t h e h s y n c in p u t . an y er r o r is use d t o s h if t t h e v c o f r e q uen c y a nd ma i n t a in lo ck b e tw e e n t h e tw o sig n a l s. the st ab i l i t y o f t h is clo c k is a ve r y im p o r t a n t ele m e n t i n p r ov iding t h e cl e a re st and mo st st abl e im age. d u r i ng e a ch p i xel t i me , t h er e is a p e r i o d d u r i n g w h ich t h e sig n a l is sle w in g f r om t h e old pixe l a m pli t ude an d s e t t l i n g a t i t s ne w va l u e . th e n t h er e is a t i m e w h en t h e in p u t v o l t a g e is s t a b le , b e fo r e t h e sig n al m u s t s l e w t o a n e w va l u e (s e e f i gur e 6). th e ra t i o o f t h e s l e w in g t i me t o th e sta b le t i m e i s a fun c ti o n o f th e ba n d wi d t h o f th e gra p h i cs d a c and the ban d wid t h o f th e t r a n smis sio n syst em (cab le and t e r m ina t ion). i t is a l s o a f u n c t i on o f t h e o v era l l p i xe l ra te . c l e a rl y , if t h e dyna mic cha r ac ter i s t ics o f t h e sy s t em r e ma in f i x e d, t h e n t h e s l e w i n g a n d s e tt l i ng t i me i s l i ke w i s e f i x e d. t h i s time m u s t b e s u b t rac t e d f r o m t h e t o tal p i xe l p e r i o d , le a v in g t h e s t a b le p e r i o d . a t hig h er p i xe l f r e q uen c ie s, th e to tal c y c l e tim e is shor te r and t h e st abl e pixel t i me a l s o b e c o me s shor te r .
ad9980 rev. 0 | page 13 of 44 pixel clock invalid sample times 04740-004 f i g u re 6. pix e l s a m p ling ti mes an y j i t t e r in t h e clo c k r e d u ces t h e p r e c ision wi t h w h ich t h e s a m p ling t i m e c a n b e de ter m i n e d and m u st a l s o b e sub t r a c t e d f r o m th e sta b le p i xe l tim e . c o n s idera b le ca r e has be e n ta k e n in th e desig n o f the ad9980 s c l o c k g e n e ra tion circ ui t t o minimize ji t t er . th e c l o c k ji t t er o f the ad9980 is 9% o r les s o f th e t o tal p i x e l tim e in all o p e r a t in g m o d e s, m aki n g t h e r e d u cti o n in t h e valid s a m p lin g t i me d u e t o ji t t er n e g l ig ib le . the p ll cha r ac t e r i s t ics a r e det e r m in e d b y t h e lo o p f i l t er desig n , t h e pll c h a r g e pum p c u r r en t, a nd t h e v c o ran g e s e t t ing. th e lo o p f i l t er desig n is i l l u st r a te d i n f i gur e 7. re commende d s e t t i n gs o f v c o ra n g e an d cha r g e p u m p c u r r en t fo r vesa st anda r d displ a y m o des a r e liste d i n t a b l e 9. c p 8nf c z 80nf r z 1.5k ? filt pv d 04740-005 f i g u re 7. pll l oop f ilt er d e t a i l f o ur p r ogra mma b l e r e g i s t ers a r e p r o v ide d t o o p t i mi ze t h e p e r f o r ma n c e o f t h e pll. th es e r e g i s t ers a r e 1. the 12-bi t divi s o r reg i st er . the in p u t h s y n c f r e q uen c ie s ca n acco mm o d a t e an y h s y n c as lo n g as t h e p r o d uc t o f t h e h s y n c and t h e pll divis o r fa l l s w i t h i n t h e o p e r a t in g r a n g e o f t h e v c o . the p ll m u l t i p lie s t h e f r e q ue n c y o f t h e h s y n c sig n a l , p r o d ucing p i xe l clo c k f r e q uen c ies in t h e ra n g e o f 10 mh z t o 95 mh z. the divis o r r e g i s t er co n t rols t h e exac t m u lt ipl i c a t i on f a c t or . t h i s re g i s t e r m a y b e s e t t o an y v a lu e betw een 2 an d 4095 as lo n g as th e o u t p u t f r eq uen c y is wi t h in ran g e . 2. the 2-bi t v c o r a n g e reg i st er . t o i m p r o v e t h e n o is e p e r f o r ma n c e o f th e ad9980, t h e v c o o p era t ing f r eq uen c y ra n g e is divide d in t o fo ur o v erla p p i n g r e g i on s. the v c o ra n g e r e g i s t er s e ts t h is o p era t in g ra n g e . th e f r e q uen c y ra n g es fo r t h e fo ur r e g i o n s a r e s h own i n t a b l e 7. table 7. vco frequency ranges p v 1 p v 0 pixel clock range (mhz) kvco gain (mhz/v) 0 0 10 to 21 150 0 1 21 to 42 150 1 0 42 to 84 150 1 1 84 to 95 150 3. the 3- b i t c h a r g e pum p c u r r en t reg i st er . this r e g i s t er va r i es t h e c u r r en t t h a t dr i v es t h e lo w-p a s s lo o p f i l t er . th e p o s s i b le c u r r en t val u es a r e lis t e d in t a b l e 8. table 8. charg e pump curren t /control bits i p 2 i p 1 i p 0 c u r r e n t ( a ) 0 0 0 5 0 0 0 1 1 0 0 0 1 0 1 5 0 0 1 1 2 5 0 1 0 0 3 5 0 1 0 1 5 0 0 1 1 0 7 5 0 1 1 1 1 5 0 0 4. the 5- b i t p h as e a d j u s t reg i st er . the phas e o f t h e g e n e r a t e d s a mp l i n g c l o c k m a y b e s h i f t e d t o l o c a t e a n o p t i mu m s a mp - lin g p o i n t wi t h i n a clo c k c y cle. the phas e ad j u st r e g i st er p r o v ides 32 p h as e-s h if t st eps o f 11.25 eac h . the h s yn c si gn al wi th a n id e n tical p h a s e sh i f t i s a v a i la b l e th r o ugh th e h s ou t p i n. phas e a d j u st is st i l l a v ai l a bl e if an e x te r n a l p i x e l c l o c k i s us ed . th e co a s t p i n o r in t e r n al c o a s t i s u s e d to a l l o w t h e pl l to c o n t i n u e to r u n a t t h e s a me f r e q u e nc y i n t h e ab s e nc e of t h e i n c o m i ng h s y n c s i g n a l or d u r i n g dist urban c es in h s y n c ( s uc h as f r o m eq ualiza tion p u ls es). this ma y be us ed d u r i ng th e v e r t ical sy n c p e r i o d o r at a n y o t h e r t i m e t h at t h e hs y n c s i g n a l i s u n av a i l a b l e . the p o la r i ty o f t h e c o ast sig n a l ma y b e s e t t h r o ug h t h e c o ast p o la r i ty r e g i st er (r eg ist e r 0x18, bi ts [6:5]). a l s o , t h e po la ri t y o f th e h s yn c si gn al ma y be se t th r o ug h th e h s yn c p o la r i ty r e g i st er (reg is ter 0x12, b i ts [5:4]). f o r bo th h s y n c a nd c o ast, a v a lue o f 1 is ac t i ve hig h . t h e in t e r n a l c o ast f u n c t i on is dr i v en o f f o f t h e vs y n c sig n a l , w h ich is ty p i ca l l y a tim e w h en h s yn c sig n als ma y be disr u p t e d wi th extra e q ualiza tio n p u ls es.
ad9980 rev. 0 | page 14 of 44 table 9. recommended vco range and charge pump and current settings for standard display formats standard resolution refresh rate (hz) horizontal frequency (khz) pixel rate (mhz) pll divider vcornge current vga 640 480 60 31.500 25.175 800 01 100 72 37.700 31.500 832 01 100 75 37.500 31.500 840 01 100 85 43.300 36.000 832 01 101 svga 800 600 56 35.100 36.000 1024 01 101 60 37.900 40.000 1056 01 100 72 48.100 50.000 1040 10 100 75 46.900 49.500 1056 10 100 85 53.700 56.250 1048 10 100 xga 1024 768 60 48.400 65.000 1344 10 101 70 56.500 75.000 1328 10 110 75 60.000 78.750 1312 10 110 80 64.000 85.500 1336 11 100 85 68.300 94.500 1376 11 100 tv 480i 30 15.750 13.510 858 00 100 480p 60 31.470 27.000 858 01 100 576i 30 15.625 13.500 864 00 100 576p 60 31.250 27.000 864 01 100 720p 60 45.000 74.250 1650 10 101 1035i 30 33.750 74.250 2200 10 101 1080i 60 33.750 74.250 2200 10 101
ad9980 rev. 0 | page 15 of 44 sync processor and vsync filter pll clock generator coast hsync hsync/vsync counter reg 26h, 27h hsync filter and regenerator channel select hsync select filtered hsync regenerated h sync set polarity set polarity set polarity set polarity activity detect ad9980 hsync0 hsync1 sogout vsyncout vsyncout datack odd/even field coast 04740-012 polarity detect mux mux mux mux activity detect polarity detect activity detect vsync0 vsync1 polarity detect mux activity detect polarity detect sogin0 sogin1 activity detect mux activity detect sync slicer sync slicer f i gure 8. s y nc p r ocessing block d i agr a m sync pro c essing the in p u ts o f t h e sy n c p r o c es sing s e c t io n o f t h e ad9980 a r e co m b in a t io ns of dig i t a l h s y n cs a nd vsy n c s , a n a l o g sy n c -on- g r e e n, o r syn c -on-y sig n als, and a n o p tio n al exter n al c o as t sig n al . f r o m th e s e sig n als i t g e nera t e s a p r e c is e , ji t t er -f r e e (9% o r les s a t 95 m h z) c l o c k f r o m i t s p l l; a n o d d-/ev e n-f i e l d sig n al; h s y n c a n d v s yn c o u t s i gn a l s ; a c o u n t o f h s yn cs pe r v s yn c ; a n d a p r og ra mma b l e so g o u t p u t . the ma i n sy n c p r o c es sin g b l o c ks a r e t h e s y n c s l ic er , syn c s e p a ra to r , h s yn c f i l t er , h s yn c r e g e n- era t o r , vsy n c f i l t er , a nd c o as t gen e r a t o r . the sy n c s l ic er ext r ac ts t h e sy nc sig n al f r o m t h e g r e e n g r a p hic s o r l u minan c e vi de o sig n a l t h a t i s co nne c t e d to t h e so gin i n p u t a nd o u t p u t s a dig i tal com p osi t e sync. th e sy n c s e p a ra t o r s tas k is t o ext r ac t vsyn c f r o m t h e com p osi t e sy n c si g n al , w h ich can co m e f r o m e i t h er t h e sy n c s l i c e r o r t h e h s y n c i n p u t. th e h s y n c f i l t er is us e d t o e l imina t e an y ext r a n e o us p u ls es f r o m t h e h s y n c o r so gin in p u ts, o u t p u t tin g a c l ea n, lo w-ji t t er sig n al tha t is a p p r o p r i a t e fo r m o d e dete c t io n a nd clo c k ge n e r a t i o n . t h e h s y n c re ge ne r a tor i s u s e d to re c r e a te a cl e a n, a l t h ou g h not l o w ji t t er , h s y n c sig n a l t h a t ca n b e us e d fo r m o d e dete c t ion an d c o u n ti n g h s yn cs pe r v s yn c . t h e v s yn c fi l t e r i s u s ed t o e l i m i - n a t e s p uri o us v s yn cs, m a in ta in a s t a b le ti m i n g r e la ti o n sh i p b e tw e e n t h e vs y n c and h s y n c o u t p ut sig n a l s, a nd ge n e r a te t h e od d / ev en f i e l d o u t p u t . th e c o a s t g e n e ra t o r cr ea t e s a r o b u s t c o as t sig n al tha t al lo ws th e p l l t o ma in t a in i t s f r eq uen c y in t h e a b s e n c e o f h s yn c p u ls es. sync slicer the p u r p os e o f t h e sy n c s l icer is t o ext r ac t t h e s y n c sig n al f r o m th e gr een gra p hi c s o r l u m i n a n c e v i deo s i gn al th a t i s c o nn ect e d t o t h e so gin i n p u t. th e sy n c s i g n al is ext r ac t e d in a t w o s t ep p r o c es s. f i rs t, t h e so g i n p u t is cla m p e d t o i t s nega t i ve p e a k , (typ ical l y 0.3 v b e lo w t h e black le v e l ). n e xt, t h e sig n al g o es t o a c o m p ar a t or w i t h a v a r i abl e t r i g ge r l e vel ( s e t b y r e g i s t e r 0 x 1 d , b i ts [7:3]), b u t no minal l y 0.128 v a b o v e t h e c l am p e d leve l . th e syn c s l icer o u t p u t is a dig i tal com p osi t e sy n c sig n al co n t ainin g bo th h s y n c an d vsyn c inf o r m a t io n (s ee f i gur e 9).
ad9980 prelim inary technical data rev. 0 | page 16 of 44 04740-015 sog input sogout output connected to hsyncin negative pulse width = 40 sample clocks composite sync at hsyncin vsyncout from sync separator ?300mv ?300mv 700mv maximum 0mv f i g u r e 9. sy n c s l ice r an d sy n c s e p a rat o r o u t p u t sync s e parat o r a s p a r t o f syn c p r o c es sin g , t h e syn c s e p a ra t o r s tas k is t o extrac t vsy n c f r o m the co m p osi t e sy n c sig n al . i t w o rks o n the ide a tha t th e vsyn c si gn a l s t a y s a c ti v e f o r a m u c h lo n g e r ti m e th a n t h e h s y n c sig n a l . by usin g a dig i t a l lo w-p a ss f i l t er a nd a dig i t a l co m p a r a t o r , i t r e je c t s p u ls es wi t h smal l d u ra tion s (s uc h as h s yn cs an d e q u a liza tio n p u ls es) a nd o n l y p a s s es p u ls es wi t h la rg e d u ra tion s, s u c h as vs y n c (s ee f i gur e 9). t h e th r e sh o l d o f th e d i g i tal co m p a r a t o r i s p r ogra m m a b l e f o r max i m u m f l ex i b i l i t y . t o p r o g ra m t h e t h r e sh old d u ra t i on, wr i t e a val u e (n) t o r e g i s t er 0x11. th e r e s u l t in g p u ls e wi d t h wi l l b e n 200 n s . s o , if n = 5 th e dig i t a l co m p a r a t o r thr e s h old wil l be 1 s. an y p u ls es les s t h a n 1 s ar e r e je c t e d , w h i l e a n y p u ls e gr ea t e r th a n 1 s pa s s e s th r o ugh . ther e a r e tw o t h in gs t o k e ep i n mi n d w h en usi n g t h e sy n c s e p a r a to r . f i rst, t h e r e su l t i n g cle a n vsy n c o u t p ut wi l l b e del a ye d f r om t h e or i g i n a l v s y n c by a du r a t i on e q u a l to t h e d i g i t a l co m p a r a t o r thr e s h old ( n 200 n s ). s e con d , t h er e is s o m e va r i a b il i t y t o the 200 n s m u l t i p l i er val u e . th e maxim u m va r i a- b i li ty o v er al l o p era t in g condi t i on s wil l b e 20% (160 n s t o 240 n s ). s i n c e no r m al vsyn c and h s y n c p u ls e wid t h s dif f er b y a fac t o r o f a b o u t 500 o r m o r e , the 20% va r i ab il i t y is n o t an is s u e . hsync filter and r e generat o r the h s y n c f i l t e r is us e d t o e l imina t e an y ext r a n e o us p u ls es f r o m t h e h s y n c or s o g i n i n put s , outputt i ng a cl e a n , l o w - j i tte r s i g n a l t h a t is a p p r o p r i a t e fo r m o de d e te c t io n and clo c k ge n e r a t i on. t h e h s yn c r e g e n e ra t o r i s used t o r e cr ea t e a c l ea n , al th o u g h n o t lo w ji tter , h s y n c sig n a l t h a t c a n b e us e d fo r m o de dete c t io n and co un tin g h s y n cs p e r vsy n c. the h s yn c r e gen e ra t o r has a hig h deg r e e o f t o lera n c e t o ext r a n e o us a n d mis s in g p u ls es o n t h e h s yn c i n p u t, b u t is n o t a p p r o p r i a t e fo r us e b y t h e pll i n c r e a t i ng t h e pi xel cl o c k d u e to j i tte r . t h e h s y n c re ge ne r a tor r u ns a u t o m a t i c a l l y an d re qu i r e s no s e t u p t o op era t e. th e h s yn c f i l t er r e q u ir es t h e s e t t i n g u p o f a f i l t er wi ndo w . th e f i l t er wi ndo w s e ts a p e r i o d i c wi n d o w o f t i m e a r o u n d t h e reg e n e ra t e d h s y n c le adin g e d g e w h er e valid h s y n c s a r e al lo w e d t o o c c u r . th e g e n e r a l ide a is t h a t ex t r a n e o us p u ls es on t h e s y nc i n put w i l l o c c u r out s i d e of t h i s f i lte r w i nd ow a n d th us wil l be f i l t er ed o u t. i n o r der t o s e t th e f i l t er win d o w timing , pro g r a m a v a lu e ( x ) in t o r e g i s t er 0x23. th e r e su l t in g f i l t er wi n d o w t i m e is x tim e s 25 n s ar o u n d t h e r e g e nera t e d h s y n c lead in g e d g e . j u s t as f o r th e sy n c sep a ra t o r thr e s h o l d m u l t i p lier , al lo w a 20% var i a n c e in the 25 n s m u l t i p lier t o acco un t f o r al l op e r a t i n g c o nd it i o ns ( 2 0 n s to 3 0 ns r a nge ) . a s e con d ou t p ut f r o m t h e h s y n c f i l t er is a s t a t u s b i t (r eg- is t e r 0x25, bi t 1) t h a t te l l s w h et her ext r a n e o us pu ls es a r e p r es en t o n the in co ming syn c sig n al . e x tra n e o us p u ls es a r e o f t e n i n c l u d e d f o r c o py prote c t i on p u r p o s e s ; t h i s s t atu s bit c a n b e us ed t o detec t t h a t . the f i l t er e d h s y n c (ra t h e r t h an t h e ra w h s y n c/ so gin sig n al) f o r pi x e l c l o c k g e n e r a t i on by t h e p l l i s c o n t ro l l e d by r e g - is t e r 0x20, b i t 2. the r e g e n e ra t e d h s y n c (ra t h e r tha n t h e ra w h s yn c / so gi n sig n al) fo r t h e s y n c p r o c es s i n g is co n t r o l l e d b y reg i st er 0x20, bi t 1. u s e o f t h e f i l t er e d h s y n c and r e g e n e ra t e d h s yn c is r e co mm en ded . s e e f i gur e 10 f o r a n il l u s t ra tio n o f a fi l t e r e d h s yn c .
ad9980 rev. 0 | page 17 of 44 hsyncout vsync filter window expec ted edge fi lter window equ a li zat i on pulses hsyncin 04740-016 f i gure 10. s y nc pr oc essing f ilter vsync filter a n d od d/even fields t h e vsy n c f i l t e r i s used t o e l im in a t e s p uri o us vsyn cs, m a in ta in a s t a b le ti m i n g r e la ti o n sh i p betw ee n t h e vsyn c a n d h s yn c o u t p ut sig n a l s, a nd ge n e r a te t h e o dd/ e v e n f i eld o u t p ut. the f i l t er w o rks b y exa m inin g t h e place m e n t o f vsyn c w i t h re sp e c t to h s y n c , and if ne c e ss ar y , sl ig h t ly shif t i ng i t i n t i me. the g o al is t o k e ep t h e vsy n c and h s y n c le adi n g e d g e s f r o m sw i t ch in g a t t h e s a me t i m e , e l i m ina t in g conf usio n as t o w h e n t h e f i rs t li ne o f a f r a m e o c c u rs. ena b le t h e vsy n c f i l t er wi t h reg i st er 0x14, bi t 2. u s e o f t h e vsy n c f i l t er is r e co m- me n d e d fo r a l l cas e s, i n cl ud i n g in t e rlac e d vi de o , a nd is r e q u ir e d w h e n usin g th e h s y n c p e r vsy n c co un t e r . f i gur e 12 il l u s t ra t e s ev en/o dd f i eld deter m in a t io n i n tw o si t u a t io n s . fi e l d 1 fi e l d 0 sy n c sepa ra to r t hre s h old fi e l d 1 fi e l d 0 23 2 1 44 31 hsyn c i n vsy n ci n vsyncou t o/e f ie l d od d f ie l d q u ad ra n t 04740-017 f i g u re 11.
ad9980 prelim inary technical data rev. 0 | page 18 of 44 fi e l d 1 fi e l d 0 syn c se para to r t h r e s hol d f i eld 1 fi eld 0 23 2 1 4 4 31 hsyn c i n vsy n ci n vsyncou t o/ e f ie l d even f i e l d q u ad ra n t 04740-018 f i gure 12. v s ync f i l t er o dd /even power m a nag e ment t o me e t displ a y re qu ire m e n ts f o r l o w st andb y p o we r , t h e ad9980 in c l udes a p o w e r - down m o de . the p o w e r - do wn s t a t e ca n be con t r o l l ed man u al l y (wi t h p i n 17 o r reg i s t er 0x1e, b i t 3), or c o m p l e tely a u toma t i c a l l y b y t h e ch i p . i f a u toma t i c c o n t rol i s s e lec t e d (0x1e, b i t 4), th e ad99 80 s decision is bas e d o n t h e s t a t us o f th e s y nc det e c t b i ts (reg is t e r 0x24, b i ts 2, 3, 6, a nd 7). i f ei t h er a n h s y n c o r a s y n c -on-g r e e n i n p u t is dete c t e d o n an y in p u t, t h e c h i p p o w e rs u p , o t h e r w is e i t p o w e rs do wn. i f ma n u al co n t r o l is desir e d , the ad9980 in c l udes th e f l exi b ili t y o f co n t r o l w i t h b o t h a de dic a te d pi n an d a r e g i ster b i t. t h e de di - c a t e d p i n a l l o w s a h a rdw a re w a t c hd o g c i rc u i t to c o n t ro l p o we r - do wn, w h ile t h e r e g i s t er b i t al lo ws p o w e r - do wn t o be con t r o l l ed b y s o f t w a r e . w i t h m a nu a l p o w e r- d o w n c o nt r o l , t h e p o l a r i t y o f t h e p o w e r - do w n p i n m u st b e s e t (0x 1 e, bi t 2) r e ga r d less o f whether th e p i n is us ed . i f un us ed , i t is r e commen ded t o s e t t h e p o la r i ty t o ac ti ve hig h and ha r d wir e t h e p i n t o g r o u n d wi t h a 10 k? r e sis t o r . i n p o w e r - do w n m o de , t h er e a r e s e v e ral cir c ui ts t h a t con t i n ue t o o p era t e n o r m al ly . th e s e r i al r e g i s t er an d s y n c det e c t cir c ui t s ma in ta in p o w e r s o tha t t h e ad9980 ca n be w o k e n u p f r o m i t s p o w e r - do wn s t a t e . th e b a n d ga p cir c ui t main ta in s p o w e r b e ca us e i t is n e e d e d fo r sy n c dete c t io n. t h e sy nc-o n-g r e e n and so go u t f u n c t i o n s co n t in ue t o o p era t e b e c a us e t h e s o g o u t o u t p ut is ne e d e d w h e n sy n c de te c t io n is p e r f o r m e d b y a s e con d a r y chi p . a l l o f t h es e cir c ui ts r e q u ir e minimal p o w e r t o o p era t e . t y p i cal s t an db y p o w e r o n the ad9980 is a b o u t 50 mw . ther e a r e tw o op t i o n s t h a t can b e s e le c t e d w h e n in p o w e r - do wn. th es e a r e co n t r o l l ed b y b i ts 0 an d 1 in reg i st er 0x1e. the f i rs t is t o det e r m i n e w h et h e r t h e so go u t p i n is p u t in hi g h im p e dan c e o r no t. i n m o st cas e s, so go ut is no t p u t i n hig h i m p e d a nc e d u r i ng nor m a l op e r a t i o n . t h e opt i o n to put so gou t i n hi g h im p e dan c e i s in cl ud e d m a in ly t o a l lo w fo r fac t o r y test in g m o de s. t h e s e c o nd o p t i on is to k e ep t h e ad99 80 p o w e r e d u p an d o n ly p u t t h e o u t p u t s in h i g h im p e dan c e . t h is opt i on i s u s e f u l w h e n t h e d a t a output s f r om t w o ch ip s are co nne c t e d o n a pcb an d t h e us er wa n t s to sw i t ch inst an t a ne ou sly b e twe e n t h e two . ta ble 10.powe r-down co nt rol a n d m o de d e s c ri pt i o ns i n p u t s mode auto po wer-do wn control 1 power-down 2 sync detect 3 powered-on or comments p o w e r - u p 1 x 1 e v e r y t h i n g p o w e r - d o w n 1 x 0 only the serial bus, sync activity detect, sog, bandgap r e ference p o w e r - u p 0 0 x e v e r y t h i n g p o w e r - d o w n 0 1 x only the serial bus, sync activity detect, sog, bandgap r e ference 1 aut o power- down con t r ol i s s e t by r e gi st er 0x1e , bi t 4. 2 pow e r- down i s c o n t r oll e d by or i n g pi n 17 wi t h r e gi st er 0 x 1e, bi t 3. th e po la r i t y of pi n 17 i s s e t b y r e gi st er 0x1e, bi t 2. 3 syn c det e ct i s d e t e rm i n ed by or i n g r e gi st er 0x24, bi t s 2, 3, 6, a n d 7.
ad9980 rev. 0 | page 19 of 44 timing diagrams t h e f o l l ow i n g t i m i ng d i ag r a ms show t h e op e r a t i o n of t h e ad9980.the o u t p u t da t a c l o c k sig n al is cr ea t e d s o tha t i t s r i sin g e d ge a l w a y s o c c u rs b e twe e n d a t a t r a n si t i on s and can b e us e d to la t c h t h e o u t p u t da t a ext e r n al l y . ther e is a pi p e lin e in t h e ad9980, which m u s t be f l us hed bef o r e valid da t a b e com e s a v a i la b l e . this m e an s six da t a s e ts a r e p r es en t e d b e fo r e valid da ta i s a v a i la b l e . t per t dcycle ?t skew datac k data hsout 04740-006 +t skew f i g u re 13. o u t p ut tim i ng datain p0 p1 p2 p5 p3 p4 p9 p6 p8 p10 p11 p7 hsin dataclk 8 clock cycle delay dataout p0 p1 p2 p3 2 clock cycle delay hs o u t 04740-007 f i g u re 14. 4: 4: 4 ti m i ng m o d e datain p0 p1 p2 p5 p3 p4 p9 p6 p8 p10 p11 p7 hsin dataclk 8 clock cycle delay cb/crout b0 r0 b2 r2 yout y0 y1 y2 y3 2 clock cycle delay 1. pixel after hsout corresonds to blue input. 2. even number of pixel delay between hsout and dataout (6 for the ad9980). hs o u t 04740-008 f i g u re 15. 4: 2: 2 ti m i ng m o d e
ad9980 prelim inary technical data rev. 0 | page 20 of 44 datain p0 p1 p2 p5 p3 p4 p9 p6 p8 p10 p11 p7 hsin dataclk 8 clock cycle delay 2 clock cycle delay ddr notes 1. output dataclk may be delayed 1/4 clock period in the registers. 2. for ddr 4:2:2 mode: timing is identical, values of f (falling edge) and r (rising edge) change. general notes 1. data delay may vary one clock cycle, depending on phase setting. 2. adcs sample input on falling edge of dataclk. 3. hsync shown is active high (edge shown is leading edge). hs o u t 04740-009 f0 r0 f1 r1 f2 r2 f3 r3 f i g u re 16. ddr ti m i ng m o d e hsync timi ng the h s y n c is p r o c es s e d in t h e ad9980 t o e l imina t e am b i gui t y i n t h e tim i n g o f th e lea d i n g e d ge wi th r e s p ect t o th e p h a s e - del a ye d pixel clo c k an d d a t a . the h s y n c i n p u t is us e d as a r e fer e n c e t o g e n e r a t e t h e p i xe l sa m p l i n g c l oc k . t h e sa m p l i n g p h a s e ca n be ad j u s t ed w i t h r e s p ec t t o h s y n c thr o ug h a f u l l 360 in 32 st eps via t h e p h as e ad j u s t r e g i st er (t o o p timize t h e p i xe l s a m p l i n g t i me). dis p l a y sys t em s us e h s y n c t o alig n m e m o r y a nd dis p l a y wr i t e c y cles, s o i t is i m p o r t a n t to ha v e a st a b le t i min g r e la t i o n shi p b e twe e n h s yn c o u t p u t (hso ut ) and t h e da ta c l o c k ( d a t a c k). thr e e thin gs ha p p en t o h s yn c in the ad9980. f i rs t, th e p o la r i ty o f h s y n c in p u t i s deter m i n e d and t h us has a k n o w n o u t p u t p o l a r i t y . t h e k n ow n output p o l a r i t y c a n b e pro g r a m m e d e i t h e r ac ti v e hig h o r ac ti v e lo w (reg ist e r 0x12, b i t 3). s e con d , hs o u t i s ali g n e d w i t h d a t a c k a n d da ta o u t p u t s. t h ir d , th e d u ra ti o n o f hso u t (in p i x e l c l o c ks) is s e t via regis t er 0 x 13. hso u t is th e sy n c sig n al tha t sh o u ld be u s ed t o dr i v e t h e r e s t o f th e displ a y s y ste m . coast timi ng i n mo st c o m p ute r s y ste m s , t h e h s y n c s i g n a l is c o n t i n u o u sly p r o v i d ed o n a ded i ca t e d w i r e . i n th ese s y s t em s , th e c o a s t i n p u t a nd f u n c t i o n a r e unne cess a r y a nd sh o u ld n o t b e us e d . i n s o m e sys t ems, h o w e v e r , h s y n c is dis t ur be d d u r i n g vsy n c. i n s o me cas e s, h s yn c p u ls es dis a p p e a r . i n o t h e r sys t em s, s u ch as th os e tha t e m p l o y co m p osi t e sy n c (csy n c ) sig n als o r em be dde d syn c -o n-gr een , h s yn c ma y in c l ud e eq uali za ti o n p u lses o r o t h e r d i stor t i ons d u r i ng v s y n c . t o a v oi d up s e tt i n g t h e cl o c k ge ne r a to r d u r i n g vsy n c, i t is im p o r t an t t o ig n o r e t h es e dist o r t i o n s. i f t h e p i xe l clo c k p l l s e es ext r a n e o us p u ls es, i t a t t e m p ts t o lo ck t o t h is ne w f r e q ue n c y , a nd wi l l cha n ge f r e q uen c y b y t h e end o f t h e vsy n c p e r i o d . i t th en ta k e s a fe w lin e s o f co r r ec t h s yn c t i min g t o r e co ver a t t h e b e g i nni n g o f a ne w f r am e, r e su l t in g i n a te a r ing o f t h e ima g e a t t h e t o p o f t h e di spla y . the c o ast i n p u t is p r o v ide d t o elimin a t e t h is p r ob lem. i t is a n a s yn c h r o n o us in p u t tha t d i sa b l e s th e pl l in p u t a n d h o ld s th e clo c k a t i t s c u r r en t f r e q ue n c y . th e pll can r u n f r e e fo r s e v e ral lin e s w i t h ou t si g n if ica n t f r e q uen c y dr if t. c o ast ca n b e ge nera t e d in t e r n al l y b y the ad9980 (s e e reg i st er 0x18) o r ca n be p r o v ide d ext e r n al l y b y t h e g r a p hics con t rol l er . w h en in t e r n al c o as t is s e lec t e d (reg is t e r 0x1 8 , b i t 7 = 0, a n d reg i st er 0x14, b i ts [7:6] t o s e lec t s o ur ce), th e vs yn c is us e d as th e b a sis fo r det e r m inin g t h e p o si tio n o f c o as t. the in t e r n al c o ast sig n a l is e n a b le d a p r og ra mme d n u m b er o f h s y n c pe ri od s be f o r e th e pe ri od i c v s yn c s i gn al ( p r e c o a s t reg i ster 0x 16) a nd dr o p p e d a p r o g r a mm e d n u m b er o f h s y n c p e r i o d s a f t e r t h e vsy n c (p os t c o a s t reg i st er 0x17). i t is r e co mme n d e d t h a t t h e vs y n c f i l t er b e ena b le d w h en usin g t h e in t e r n al c o as t f u n c tion t o al lo w the ad9980 to p r ecis e l y det e r m i n e t h e n u m b er o f h s yncs/vsy n c and t h eir lo ca t i on. i n ma n y a p plic a t ion s w h er e disr u p t i o n s o c c u r an d c o ast is us e d , va l u es o f 2 fo r th e pr e c o a st an d 10 fo r p o st co ast a r e suf f i cien t to a v o i d m o st ext r a n e o us p u ls es. output formatter t h e o u t p u t f o r m a t t e r is ca p a b l e o f g e n e ra t i n g sev e ral o u t p u t fo r m a t s t o b e p r es en t e d t o t h e 2 4 da t a o u t p ut p i n s . th e o u t p u t fo r m a t s a nd t h e p i n as sig n m e n t s fo r e a c h fo r m a t a r e lis t e d in t a b l e 11. a l s o , t h er e a r e s e v e ral clo c k o p t i o n s for t h e o u t p u t clo c k. t h e us er ma y s e le c t t h e pixel clo c k, a 90 phas e- shif te d p i xel clo c k, a 2 p i xel clo c k, o r a f i xe d f r e q uen c y 40 mh z clo c k fo r t e s t p u r p os es. th e ou t p u t cl o c k ma y als o b e in v e r t e d . d a t a output i s av ai l a bl e a s a 2 4 - p i n rg b or y c b c r , or i f e i t h e r 4:2:2 o r 4:4:4 d d r is s e lec t e d , a s e co nda r y c h a nne l is a v a i lab l e. this s e conda r y c h a n n e l is al wa ys 4:2:2 d d r a nd al lo ws th e f l ex i b i l i t y o f ha v i n g a s e con d ch a nnel wi t h t h e s a me vi de o da t a t h a t c a n b e ut i l i z e d by anot he r d i spl a y or a stor age d e v i c e . d e p e nd i n g o n t h e c h oi c e of output mo d e s , t h e pr i m ar y output ca n be 24 p i n s , 16 p i n s o r as f e w as 12 p i n s .
ad9980 rev. 0 | page 21 of 44 mode descriptions ? 4:4:4all channels come out with their 8 data bits at the same time. data is aligned to the negative edge of the clock for easy capture. this is the normal 24-bit output mode for rgb or 4:4:4 ycbcr. ? 4:2:2red and green channels contain 4:2:2 formatted data (16 pins) with y data on the green channel and cb, cr data on the red channel. data is aligned to the negative edge of the clock. the blue channel contains the secondary channel with cb, y, cr, y formatted ddr 4:2:2 data. the data edges are aligned to both edges of the pixel clock, so use of the 90 clock may be necessary to capture the ddr data. ? 4:4:4 ddrthis mode puts out full 4:4:4 data on 12 bits of the red and green channels thus saving 12 pins. the first half (rgb [11:0]) of the 24-bit data is sent on the rising edge and the second half (rgb [23:12]) is sent on the falling edge. the 4:2:2 ddr data is sent on the blue channel, as in 4:2:2 mode. rgb [23:0] = r [7:0] + g [7:0] + b [7:0], so rgb [23:12] = r [7:0] + g [7:4] and rgb [11:0] = g [3:0] + b [7:0] table 11. output formats port red green blue bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 4:4:4 red/cr green/y blue/cb 4:2:2 1 cb, cr y ddr 4:2:2 cb, cr y, y 4:4:4 ddr ddr 2 g [3:0] ddr b [7:4] ddr b [3:0] n/a ddr 4:2:2 cb, cr ddr 2 r [7:0] ddr g [7:4] n/a ddr 4:2:2 y, y 1 for 4:2:2 modes the first item in the list is the first pixel after hsync. 2 arrows in the table indicate clock edge. rising edge of clock = , falling edge = .
ad9980 preliminary technical data rev. 0 | page 22 of 44 two-wire serial register map the ad9980 is initialized and controlled by a set of registers, wh ich determine the operating modes. an external controller is employed to write and read the control registers through the two-wire serial interface port. table 12. control register map hexadecimal address read and write or read only bits default value register name description 0x00 ro 7:0 chip revision an 8-bit register that represents the silicon revision level. 0x01 r/w 7:0 0110 1001 pll div msb this register is for bits [11:4] of the pll divider. larger values mean the pll operates at a faster rate. this register should be loaded first whenever a change is needed. (this will give the pll more time to lock). 1 0x02 r/w 7:4 1101 **** pll div lsb bits [7:4] lsbs of the pll divider word. links to the pll div msb to make a 12-bit register. 1 0x03 r/w 7:6 01** **** vco/cpmp bits [7:6] vco range. selects vco frequency range. (see pll description). 5:3 **00 1*** bits [5:3] charge pump current. va ries the current that drives the low-pass filter. (see pll description). 2 **** *0** bit 2. external clock enable 0x04 r/w 7:3 1000 0*** phase adjust adc clock phase adjustment. larger values mean more delay. (1 lsb = t/32). 0x05 r/w 6:0 *100 0000 red gain msb 7-bit red channel gain control. controls the adc input range (contrast) of each respective channel. bigger values give less contrast. 2 0x06 r/w 7:0 0000 0000 must be written to 0x00 following a write of register 0x05 for proper operation. 0x07 r/w 6:0 *100 0000 green gain msb 7-bit green channel gain control. controls the adc input range (contrast) of each respective channel. bigger values give less contrast. 2 0x08 r/w 7:0 0000 0000 must be written to 0x00 following a write of register 0x07 for proper operation. 0x09 r/w 6:0 *100 0000 blue gain msb 7-bit blue channel gain contro l. controls the adc input range (contrast) of each respective channel. bigger values give less contrast. 2 0x0a r/w 7:0 0000 0000 must be written to 0x00 following a write of register 0x09 for proper operation. 0x0b r/w 7:0 0100 0000 red offset msb 8-bit msb of the red channel offset control. controls the dc offset (brightness) of each respective channel. bigger values decrease brightness. 1 0x0c r/w 7 0*** **** red offset linked with 0x0b to form the 9-bi t red offset that controls the dc offset (brightness) of the re d channel in auto-offset mode. 0x0d r/w 7:0 0100 0000 green offset msb 8-bit msb of the green channel offset control. controls the dc offset (brightness) of each re spective channel. bigger values decrease brightness. 1 0x0e r/w 7 0*** **** green offset linked with 0x0d to form the 9- bit green offset that controls the dc offset (brightness) of the gr een channel in auto-offset mode. 0x0f r/w 7:0 0100 0000 blue offset msb 8-bit msb of the red channel offset control. controls the dc offset (brightness) of each respective channel. bigger values decrease brightness. 1 0x10 r/w 7 0*** **** blue offset linked with 0x0f to form the 9-bit blue offset that controls the dc offset (brightness) of the blue channel in auto-offset mode. 0x11 r/w 7:0 0010 0000 sync separator threshold this register sets the threshold of the sync separators digital comparator.
ad9980 rev. 0 | page 23 of 44 hexadecimal address read and write or read only bits default value register name description 0x12 r/w 7 0*** **** hsync control active hsync override. 0 = the chip determines the active hsync source. 1 = the active hsync source is set by 0x12, bit 6. 6 *0** **** selects the source of the hsync for pll and sync processing. this bit is used only if 0x12, bit 7 is set to 1 or if both syncs are active. 0 = hsync is from hsync input pin. 1 = hsync is from sog. 5 **0* **** hsync polarity override. 0 = the chip selects the hsync input polarity. 1 = the polarity of the input hsync is controlled by 0x12, bit 4. this applies to both hsync0 and hsync1. 4 ***1 **** hsync input polarity: this bit is used only if 0x12, bit 5 is set to 1. 0 = active low input hsync. 1 = active high input hsync. 3 **** 1*** sets the polarity of the hsync output signal. 0 = active low hsync output. 1 = active high hsync output. 0x13 r/w 7:0 0010 0000 hsync duration sets the number of pixel cloc ks that hsync out is active. 0x14 r/w 7 0*** **** vsync control active vsync override. 0 = the chip determines the active vsync source. 1 = the active vsync source is set by 0x14, bit 6. 6 *0** **** selects the source of vsync for the sync processing. this bit is used only if 0x14, bit 7 is set to 1. 0 = vsync is from the vsync input pin. 1 = vsync is from the sync separator. 5 **0* **** vsync polarity override. 0 = the chip selects the input vsync polarity. 1 = the polarity of the input vsync is set by 0x14, bit 4. this applies to both vsync0 and vsync1. 4 ***1 **** vsync input polarity: this bit is used only if 0x14, bit 5 is set to 1. 0 = active low input vsync. 1 = active high input vsync. 3 **** 1*** sets the polarity of the output vsync signal. 0 = active low output vsync. 1 = active high output vsync. 2 **** *0** 0 = the vsync filter is disabled. 1 = the vsync filter is enabled. this needs to be enabled when using the hsync to vsync counter. 1 **** **0* enables the vsync duration block. th is is designed to be used with the vsync filter. 0 = vsync output duration is unchanged. 1 = vsync output duration is set by register 0x15. 0x15 r/w 7:0 0000 1010 vsync duration sets the number of hsyncs that vs ync out is active. this is only used if 0x14, bit 1 is set to 1. 0x16 r/w 7:0 0000 0000 precoast the number of hsync periods to coast prior to vsync. 0x17 r/w 7:0 0000 0000 postcoast the number of hsync periods to coast after vsync. 0x18 r/w 7 0*** **** coast and clamp control coast source. selects the source of the coast signal. 0 = using internal coast generated from vsync. 1 = using external coast signal from external coast pin. 6 *0** **** coast polarity override. 0 = the chip selects the external coast polarity. 1 = the polarity of the external coas t signal is set by 0x18, bit 5.
ad9980 preliminary technical data rev. 0 | page 24 of 44 hexadecimal address read and write or read only bits default value register name description 5 **1* **** coast input polarity. this bit is used only if 0x18, bit 6 is set to 1. 0 = active low external coast. 1 = active high external coast. 4 ***0 **** clamp source select. 0 = use the internal clamp generated from hsync. 1 = use the external clamp signal. 3 **** 0*** red clamp. 0 = clamp the red channel to ground. 1 = clamp the red channel to midscale. 2 **** *0** green clamp. 0 = clamp the green channel to ground. 1 = clamp the green channel to midscale. 1 **** **0* blue clamp. 0 = clamp the blue channel to ground. 1 = clamp the blue channel to midscale. 0 **** ***0 must be set to 0 for proper operation. 0x19 r/w 7:0 0000 1000 clamp placement places the clamp signal an integer of clock periods after the trailing edge of the hsync signal. 0x1a r/w 7:0 0010 0000 clamp duration number of clock periods that the clamp signal is actively clamping. 0x1b r/w 7 0*** **** clamp and offset external clamp polarity override. 0 = the chip selects the clamp polarity. 1 = the polarity of the clamp signal is set by 0x1b, bit 6. 6 *1** **** external clamp input polarity. this bi t is used only if 0x1b, bit 7 is set to 1. 0 = active low external clamp. 1 = active high external clamp. 5 **0* **** 0 = auto-offset is disabled. 1 = auto-offset is enabled (offs ets become the desired clamp code). 4:3 ***1 1*** this selects how often the auto-o ffset circuit operates. 00 = every clamp; 01 = 16 clamps; 10 = every 64 clamps; 11 = every vsync. 2:0 **** *011 must be written to default (011) for proper operation. 0x1c r/w 7:0 1111 1111 testreg0 must be set to 0xff for proper operation. 0x1d r/w 7:3 0111 1*** sog control sog slicer threshold. sets the voltage level of the sog slicers comparator. 2 **** *0** sogout polarity. sets the polarity of the signal on the sogout pin. 0 = active low sogout. 1 = active high sogout. 1:0 **** **00 sogout select. 00 = raw sog from sync slicer (sog0 or sog1). 01 = raw hsync (hsync0 or hsync1). 10 = regenerated sync from sync filter. 11 = filtered sync from sync filter. 0x1e r/w 7 *** **** power channel select override. 0 = the chip determines whic h input channels to use. 1 = the input channel selection is determined by 0x1e, bit 6. 6 *0** **** channel select. input channel select: this is used only if 0x1e, bit 7 is set to 1, or if syncs are present on both channels. 0 = channel 0 syncs and data are selected. 1 = channel 1 syncs and data are selected.
ad9980 rev. 0 | page 25 of 44 hexadecimal address read and write or read only bits default value register name description 5 **1* **** programmable bandwidth. 0 = low analog input bandwidth. 1 = high analog input bandwidth. 4 ***1 **** power-down control select. 0 = manual power-down control. 1 = auto power-down control. 3 **** 0*** power-down. 0 = normal operation. 1 = power-down. 2 **** *0** power-down pin polarity. 0 = active low. 1 = active high. 1 **** **0* power-down fast sw itching control. 0 = normal power-down operation. 1 = the chip stays powered up an d the outputs are put in high impedance mode. 0 **** ***0 sogout high impedance control. 0 = sogout operates as no rmal during power-down. 1 = sogout is in high impedance during power-down. 0x1f r/w 6:5 *00* **** output select 1 output mode. 00 = 4:4:4 output mode. 01 = 4:2:2 output mode. 10 = 4:4:4 C ddr output mode. 4 ***1 **** primary output enable. 0 = primary output is in high impedance state. 1 = primary output is enabled. 3 **** 0*** secondary output enable. 0 = secondary output is in high impedance state. 1 = secondary output is enabled. 2:1 **** *10* output drive strength. 00 = low output drive strength. 01 = medium low output drive strength. 10 = medium high output drive strength. 11 = high output drive strength. applies to all outputs except vsout. 0 **** ***0 output clock invert. 0 = noninverted pixel clock. 1 = inverted pixel clock. applies to all clocks output on datack. 0x20 r/w 7:6 00** **** output select 2 output clock select. 00 = pixel clock. 01 = 90 phase shifted pixel clock. 10 = 2 pixel clock. 11 = 40 mhz internal clock. 5 **0* **** output high impedance. 0 = normal outputs. 1 = all outputs except sogout in high impedance mode. 4 ***0 **** sog high impedance. 0 = normal sog output 1 = sogout pin is in high impedance mode. 3 **** 1*** field output polarity. sets the polarity of the field output signal. 0 = active low => even field, active high => odd field. 1 = active low => odd field, active high => even field. 2 **** *0** pll sync filter enable. 0 = pll uses raw hsync/sog. 1 = pll uses filtered hsync/sog.
ad9980 preliminary technical data rev. 0 | page 26 of 44 hexadecimal address read and write or read only bits default value register name description 1 **** **1* sync processing input select. selects the sync source for the sync processor. 0 = sync processing uses raw hsync/sogin. 1 = sync processing uses regenerated hsync from sync filter. 0 **** ***1 must be set to 1 for proper operation. 0x21 r/w 7:0 0010 0000 must be set to default for proper operation. 0x22 r/w 7:0 0011 0010 must be set to default for proper operation. 0x23 r/w 7:0 0000 1010 sync filter window width sets the window of time around the regenerated hsync leading edge (in 25 ns steps) that sync pulses are allowed to pass through. 0x24 ro 7 _*** **** sync detect hsync0 detection bit. 0 = hsync0 is not active. 1 = hsync0 is active. 6 *_** **** hsync1 detection bit. 0 = hsync 1 is not active. 1 = hsync 1 is active. 5 **_* **** vsync 0 detection bit. 0 = vsync0 is not active. 1 = vsync0 is active. 4 ***_ **** vsync1 detection bit. 0 = vsync1 is not active. 1 = vsync1 is active. 3 **** _*** sog0 detection bit. 0 = sog0 is not active. 1 = sog0 is active. 2 **** *_** sog1 detection bit. 0 = sog1 is not active. 1 = sog1 is active. 1 **** **_* coast detection bit. 0 = external coast is not active. 1 = external coast is active. 0 **** ***_ clamp detection bit. 0 = external clamp is not active. 1 = external clamp is active. 0x25 ro 7 _*** **** sync polarity detect hsync0 polarity. 0 = hsync0 polarity is active low. 1 = hsync0 polarity is active high. 6 *_** **** hsync1 polarity. 0 = hsync1 polarity is active low. 1 = hsync1 polarity is active high. 5 **_* **** vsync0 polarity. 0 = vsync0 polarity is active low. 1 = vsync0 polarity is active high. 4 ***_ **** vsync1 polarity. 0 = vsync1 polarity is active low. 1 = vsync1 polarity is active high. 3 **** _*** coast polarity. 0 = external coast polarity is active low. 1 = external coast polarity is active high. 2 **** *_** clamp polarity. 0 = external clamp polarity is active low. 1 = external clamp polarity is active high. 1 **** **_* extraneous pulses detected. 0 = no equalization pulses detected on hsync. 1 = extraneous pulses detected on hsync.
ad9980 rev. 0 | page 27 of 44 hexadecimal address read and write or read only bits default value register name description 0x26 ro 7:0 hsyncs per vsync msbs msbs of hsyncs per vsync count. 0x27 ro 7:4 hsyncs per vsync lsbs lsbs of hsyncs per vsync count. 0x28 r/w 7:0 1011 1111 testreg1 must be written to 0xbf for proper operation. 0x29 r/w 7:0 0000 0010 testreg2 must be written to 0x02 for proper operation. 0x2a ro 7:0 testreg3 read-only bits for future use. 0x2b ro 7:0 testreg4 read-only bits for future use. 0x2c r/w 7:5 000* **** offset hold must be written to default for proper operation. 4 ***0 **** auto-offset hold. disables the auto-offset and holds the feedback result. 1 = one time update. 0 = continuous update. 3:0 **** 0000 must be written to default for proper operation. 0x2d r/w 7:0 1111 0000 testreg5 must be written to 0xe8 for proper operation. 0x2e r/w 7:0 1111 0000 testreg6 must be written to 0xe0 for proper operation. 1 functions with more than eight control bits, such as pll divide ratio, gain, and offset, are only updated when the lsbs are wr itten to (for example, register 0x02 for pll divide ratio). 2 gain registers (register 0x05, register 0x07 and register 0x09) when written to must each be followed with a write to their ne xt register: register 0x05 and register 0x06, register 0x07 and register 0x08, and register 0x09 and register 0x0a.
ad9980 preliminary technical data rev. 0 | page 28 of 44 detailed 2-wire serial control register descriptions chip identification 0x00 7:0 chip revision an 8-bit register which represents the silicon revision . pll divider control 0x01 7:0 pll divide ratio msbs the eight msbs of the 12-bit pll divide ratio plldiv. the pll derives a pixel clock from the incoming hsync signal. the pixel clock frequency is then divided by an integer value, such that the output is phase-locked to hsync. this plldiv value determines the number of pixel times (pixels plus horizontal blanking overhead) per line. this is typically 20% to 30% more than the number of active pixels in the display. the 12-bit value of the pll divider supports divide ratios from 2 to 4095 as long as the output frequency is within range. the higher the value loaded in this register, the higher the resulting clock frequency with respect to a fixed hsync frequency. vesa has established some standard timing specifications, which will assist in determining the value for plldiv as a function of horizontal and vertical display resolution and frame rate (see table 9). however, many computer systems do not conform precisely to the recommendations and these numbers should be used only as a guide. the display system manufacturer should provide automatic or manual means for optimizing plldiv. an incorrectly set plldiv usually produces one or more vertical noise bars on the display. the greater the error, the greater the number of bars produced. the power-up default value of plldiv is 1693. plldivm = 0x69, plldivl = 0xdx. the ad9980 updates the full divide ratio only when the lsbs are written. writing to this register by itself does not trigger an update. 0x02 7:4 pll divide ratio lsbs the four lsbs of the 12-bit pll divide ratio plldiv. the power-up default value of plldiv is 1693. plldivm = 0x69, plldivl = 0xdx. clock generator control 0x03 7:6 vco range select two bits that establish the operating range of the clock generator. vcornge must be set to correspond to the desired operating frequency (incoming pixel rate). the pll gives the best jitter performance at high frequencies. for this reason, in order to output low pixel rates and still get good jitter performance, the pll actually operates at a higher frequency but then divides down the clock rate afterwards. see table 13 for the pixel rates for each vco range setting. the pll output divisor is automatically selected with the vco range setting. the power-up default value is 01. table 13. vco ranges vco range pixel rates 00 10 to 21 01 21 to 42 10 42 to 84 11 84 to 95 0x03 5:3 charge pump current three bits that establish the current driving the loop filter in the clock generator. the current must be set to correspond with the desired operating frequency. the power-up default value is current = 001. table 14. charge pump currents ip2 ip1 ip0 current 0 0 0 50 0 0 1 100 0 1 0 150 0 1 1 250 1 0 0 350 1 0 1 500 1 1 0 750 1 1 1 1500 0x03 2 external clock enable this bit determines the source of the pixel clock. table 15. external clock select settings extclk function 0 internally generated clock 1 externally provided clock signal a logic 0 enables the internal pll that generates the pixel clock from an externally provided hsync. a logic 1 enables the external extclk input pin. in this mode, the pll divide ratio (plldiv) is ignored. the clock phase adjust (phase) is still functional. the power-up default value is extclk = 0.
ad9980 rev. 0 | page 29 of 44 phase adjust 0x04 7:3 phase adjustment for the dll to generate the adc clock. a 5-bit value that adjusts the sampling phase in 32 steps across one pixel time. each step represents an 11.25 shift in sampling phase. the power up default is 16. input gain 0x05 6:0 red channel gain adjust the 7-bit red channel gain control. the ad9980 can accommodate input signals with a full-scale range of 0.5 v to 1.0 v p-p. setting the red gain to 127 corresponds to an input range of 1.0 v. a red gain of 0 establishes an input range of 0.5 v. note that increasing red gain results in the picture having less contrast (the input signal uses fewer of the available converter codes). values written to this register will not be updated until the following register (register 0x06) has been written to 0x00. the power- up default is 100 0000. 0x07 6:0 green channel gain adjust the 7-bit green channel gain control. see red channel gain adjust above. register update requires writing 0x00 to register 0x08. 0x09 6:0 blue channel gain adjust the 7-bit blue channel gain control. see red channel gain adjust above. register update requires writing 0x00 to register 0x0a. input offset 0x0b 7:0 red channel offset the 8-bit msb of the red channel offset control. along with the lsb in the following register, there are nine bits of dc offset control in the red channel. the offset control shifts the analog input, resulting in a change in brightness. note that the function of the offset register depends on whether auto-offset is enabled (register 0x1b, bit 5). if auto-offset is disabled, the lower seven bits of the offset registers (for the red channel register 0x0b, bits [5:0] plus register 0x0c, bit 7) control the absolute offset added to the channel. the offset control provides a 63 lsbs of adjustment range, with one lsb of offset corresponding to 1 lsb of output code. if auto-offset is enabled, the 9-bit offset (comprised of the 8 bits of the msb register and bit 7 of the following register) determines the clamp target code. the 9-bit offset consists of one sign bit plus eight bits. if the register is programmed to 130, then the output code will be equal to 130 at the end of the clamp period. incrementing the offset register setting by 1 lsb will add 1 lsb of offset, regardless of the auto- offset setting. values written to this register are not updated until the lsb register (register 0x0c) has also been written. 0x0c 7 red channel offset lsb the lsb of the red channel offset control which combines with the eight bits of msb in the previous register to make nine bits of offset control. 0x0d 7:0 green channel offset the 8-bit green channel offset control. see red channel offset (0x0b). update of this register occurs only when register 0x0e is also written. 0x0e 7 green channel offset lsb the lsb of the green channel offset control which combines with the eight bits of msb in the previous register to make nine bits of offset control. 0x0f 7:0 blue channel offset the 8-bit blue channel offset control. see red channel offset (0x0b). update of this register occurs only when register 0x10 is also written. 0x10 7 blue channel offset lsb the lsb of the blue channel offset control which combines with the eight bits of msb in the previous register to make nine bits of offset control. hsync controls 0x11 7:0 sync separator threshold this register sets the threshold of the sync separators digital comparator. the value written to this register is multiplied by 200 ns to get the threshold value. therefore, if a value of 5 is written, the digital comparator threshold is 1 s and any pulses less than 1 s are rejected by the sync separator. there is some variability to the 200 ns multiplier value. the maxi- mum variability over all operating conditions is 20% (160 ns to 240 ns). since normal vsync and hsync pulse widths differ by a factor of about 500 or more, the 20% variability is not an issue. the power-up default value is 32 ddr.
ad9980 preliminary technical data rev. 0 | page 30 of 44 0x12 7 hsync source override this is the active hsync override. setting this to 0 allows the chip to determine the active hsync source. setting it to 1 uses bit 6 of register 0x12 to determine the active hsync source. power-up default value is 0. table 16. active hsync source override override result 0 hsync source determined by chip 1 hsync source determined by user register 0x12, bit 6 0x12 6 hsync source this bit selects the source of the hsync for pll and sync processing only if bit 7 of register 0x12 is set to 1 or if both syncs are active. setting this bit to 0 specifies the hsync from the input pin. setting it to 1 selects hsync from sog. power-up default is 0. table 17. active hsync select settings select result 0 hsync input 1 hsync from sog 0x12 5 hsync input polarity override this bit sets whether the chip selects the hsync input polarity or if it is specified. setting this bit to 0 allows the chip to automatically select the polarity of the input hsync. setting this bit to 1 indicates that bit 4 of register 0x12 specifies the polarity. power-up default is 0. table 18. hsync input polarity override settings override bit result 0 hsync polarity determined by chip 1 hsync polarity determined by user register 0x12, bit 4 0x12 4 input hsync polarity if bit 5 of register 0x12 is 1, the value of this bit specifies the polarity of the input hsync. setting this bit to 0 indicates an active low hsync; setting this bit to 1 indicates an active high hsync. power-up default is 1. table 19. hsync input polarity settings hsync polarity bit result 0 hsync input polarity is negative 1 hsync input polarity is positive 0x12 3 hsync output polarity this bit sets the polarity of the hsync output. setting this bit to 0 sets the hsync output to active low. setting this bit to 1 sets the hsync output to active high. power-up default setting is 1. table 20. hsync output polarity settings hsync output polarity bit result 0 hsync output polarity is negative 1 hsync output pola rity is positive 0x13 7:0 hsync duration an 8-bit register that sets the duration of the hsync output pulse. the leading edge of the hsync output is triggered by the internally-generated, phase-adjusted pll feedback clock. the ad9980 then counts a number of pixel clocks equal to the value in this register. this triggers the trailing edge of the hsync output, which is also phase-adjusted. vsync controls 0x14 7 vsync source override this is the active vsync override. setting this to 0 allows the chip to determine the active vsync source. setting it to 1 uses bit 6 of register 0x14 to determine the active vsync source. power-up default value is 0. table 21. active vsync source override override result 0 vsync source determined by chip 1 vsync source determined by user register 0x14, bit 6 0x14 6 vsync source this bit selects the source of vsync for sync processing only if bit 7 of register 0x14 is set to 1. setting bit 6 to 0 specifies vsync from the input pin. setting it to 1 selects vsync from the sync separator. power-up default is 0. table 22. active vsync select settings select result 0 vsync input 1 vsync from sync separator 0x14 5 vsync input polarity override this bit sets whether the chip selects the vsync input polarity or if it is specified. setting this bit to 0 allows the chip to automatically select the polarity of the input vsync. setting this bit to 1 indicates that bit 4 of register 0x14 specifies the polarity. power-up default is 0. table 23. vsync input polarity override settings override bit result 0 vsync polarity determined by chip 1 vsync polarity determined by user register 0x14, bit 4
ad9980 rev. 0 | page 31 of 44 0x14 4 input vsync polarity if bit 5 of register 0x14 is 1, the value of this bit specifies the polarity of the input vsync. setting this bit to 0 indicates an active low vsync; setting this bit to 1 indicates an active high vsync. power-up default is 1. table 24. vsync input polarity settings override bit result 0 vsync input polarity is negative 1 vsync input polarity is positive 0x14 3 vsync output polarity this bit sets the polarity of the hsync output. setting this bit to 0 sets the hsync output to active low. setting this bit to 1 sets the hsync output to active high. power-up default is 1. table 25. vsync output polarity settings vsync output polarity bit result 0 vsync output polarity is negative 1 vsync output polarity is positive 0x14 2 vsync filter enable this bit enables the vsync filter allowing precise placement of the vsync with respect to the hsync and facilitating the correct operation of the hsyncs/vsync count. table 26. vsync filter enable vsync filter bit result 0 vsync filter disabled 1 vsync filter enabled 0x14 1 vsync duration enable this enables the vsync duration block, which is designed to be used with the vsync filter. setting the bit to 0 leaves the vsync output duration unchanged. setting the bit to 1 sets the vsync output duration based on register 0x15. power-up duration is 0. table 27. vsync duration enable vsync duration bit result 0 vsync output durati on is unchanged 1 vsync output duration is set by register 0x15 0x15 7:0 vsync duration this is used to set the output duration of the vsync, and is designed to be used with the vsync filter. this is valid only if register 0x14, bit 1 is set to 1. power-up default is 10. coast and clamp controls 0x16 7:0 precoast this register allows the internally generated coast signal to be applied prior to the vsync signal. this is necessary in cases where pre-equalization pulses are present. the step size for this control is one hsync period. for precoast to work correctly, it is necessary for the vsync filter (register 0x14, bit 2) and sync processing filter (register 0x20, bit 1) both to be either enabled or disabled. the power-up default is 00. 0x17 7:0 postcoast this register allows the internally generated coast signal to be applied following the vsync signal. this is necessary in cases where post equalization pulses are present. the step size for this control is one hsync period. for postcoast to work correctly, it is necessary for the vsync filter (register 0x14, bit 2) and sync processing filter (register 0x20, bit 1) both to be either enabled or disabled. the power-up default is 00. 0x18 7 coast source this bit is used to select the active coast source. the choices are the coast input pin or vsync. if vsync is selected, the additional decision of using the vsync input pin or the output from the sync separator needs to be made (register 0x14, bits [7: 6]). table 28. coast source selection settings select result 0 vsync (internal coast) 1 coast input pin 0x18 6 coast polarity override this register is used to override the internal circuitry that determines the polarity of the coast signal going into the pll. the power-up default setting is 0. table 29. coast polarity override settings override bit result 0 coast polarity determined by chip 1 coast polarity determined by user 0x18 5 input coast polarity this register sets the input coast polarity when bit 6 of register 0x18 = 1. the power-up default setting is 1. table 30. coast polarity settings coast polarity bit result 0 coast polarity is negative 1 coast polarity is positive
ad9980 preliminary technical data rev. 0 | page 32 of 44 0x18 4 clamp source this bit determines the source of clamp timing. a 0 enables the clamp timing circuitry controlled by clamp placement and clamp duration. the clamp posi- tion and duration is counted from the leading edge of hsync. a 1 enables the external clamp input pin. the three channels are clamped when the clamp signal is active. the polarity of clamp is determined by the clamp polarity bit. the power-up default setting is 0. table 31. clamp source selection settings clamp source result 0 internally generated clamp 1 externally provided clamp signal 0x18 3 red clamp select this bit determines whether the red channel is clamped to ground or to midscale. the power-up default setting is 0. table 32. red clamp select settings clamp result 0 clamp to ground 1 clamp to midscale 0x18 2 green clamp select this bit determines whether the green channel is clamped to ground or to midscale. the power-up default setting is 0. table 33. green clamp select settings clamp result 0 clamp to ground 1 clamp to midscale 0x18 1 blue clamp select this bit determines whether the blue channel is clamped to ground or to midscale. the power-up default setting is 0. table 34. blue clamp select settings clamp result 0 clamp to ground 1 clamp to midscale 0x19 7:0 clamp placement an 8-bit register that sets the position of the internally generated clamp. when extclmp = 0 (register 0x18, bit 4), a clamp signal is generated internally at a position established by the clamp placement register (0x19) and for a duration set by the clamp duration register (0x1a). clamping starts a clamp placement (register 0x19) count of pixel periods after the trailing edge of hsync. the clamp placement may be programmed to any value between 1 and 255. a value of 0 is not supported. the clamp should be placed during a time that the input signal presents a stable black-level reference, usually the back porch period between hsync and the image. when extclmp = 1, this register is ignored. power-up default setting is 8. 0x1a 7:0 clamp duration an 8-bit register that sets the duration of the internally generated clamp. when extclmp = 0 (register 0x18, bit 4), a clamp signal is generated internally at a position established by the clamp placement register and for a duration set by the clamp duration register. clamping begins a clamp placement (register 0x19) count of pixel peri- ods after the trailing edge of hsync. the clamp dura- tion may be programmed to any value between 1 and 255. a value of 0 is not supported. for the best results, the clamp duration should be set to include the majority of the black reference signal time that follows the hsync signal trailing edge. insufficient clamping time can produce brightness changes at the top of the screen, and a slow recovery from large changes in the average picture level (apl), or brightness. when extclmp = 1, this register is ignored. power-up default setting is 20 ddr. 0x1b 7 clamp polarity override this bit is used to override the internal circuitry that determines the polarity of the clamp signal. the power-up default setting is 0. table 35. clamp polarity override settings override bit result 0 clamp polarity determined by chip 1 clamp polarity determined by user register 0x1b, bit 6 0x1b 6 input clamp polarity this bit indicates the polarity of the clamp signal only if bit 7 of register 0x1b = 1. the power-up default setting is 1. table 36. clamp polarity override settings clmpol result 0 active low 1 active high
ad9980 rev. 0 | page 33 of 44 0x1b 5 auto-offset enable this bit selects between auto-offset mode and manual offset mode (auto-offset disabled). see the section on auto-offset operation. the power-up default setting is 0. table 37. auto-offset settings auto-offset result 0 auto-offset is disabled 1 auto-offset is enab led (manual offset mode) 0x1b 4:3 auto-offset update frequency these bits control how often the auto-offset circuit is updated (if enabled). updating every 64 hsyncs is recommended. the power-up default setting is 11. table 38. auto-offset update mode clamp update result 00 update offset every clamp period 01 update offset every 16 clamp periods 10 update offset every 64 clamp periods 11 update offset every vsync periods 0x1b 2:0 must be written to 011 for proper operation. 0x1c 7:0 testreg0 must be written to 0xff for proper operation. sog control 0x1d 7:3 sog comparator threshold this register allows the comparator threshold of the sog slicer to be adjusted. this register adjusts it in steps of 8 mv, with the minimum setting equaling 8 mv and the maximum setting equaling 256 mv. the power-up default setting is 15 and corresponds to a threshold value of 128 mv. 0x1d 2 sog output polarity this bit sets the polarity of the sogout signal. the power-up default setting is 0. table 39. sogout polarity settings sogout result 0 active low 1 active high 0x1d 1:0 sog output select these register bits control the output on the sogout pin. options are the raw sog from the slicer (this is the unprocessed sog signal produced from the sync slicer), the raw hsync, the regenerated sync from the sync filter that can generate missing syncs either due to coasting or dropout, and the filtered sync which excludes extraneous syncs not occurring within the sync filter window. the power-up default setting is 0. table 40. sogout polarity settings sogout select function 00 raw sog from sync slicer (sog0 or sog1) 01 raw hsync (hsync0 or hsync1) 10 regenerated sync from sync filter 11 filtered sync from sync filter input and power control 0x1e 7 channel select override this bit provides an override to the automatic input channel selection. power-up default setting is 0. table 41. channel source override override result 0 channel input source determined by chip 1 channel input source determined by user register 0x1e, bit 6 0x1e 6 channel select this bit selects the active input channel if register 0x1e, bit 7 = 1. this selects between channel 0 data and syncs or channel 1 data and syncs. power-up default setting is 0. table 42. channel select channel select result 0 channel 0 data and syncs are selected 1 channel 1 data and syncs are selected 0x1e 5 programmable bandwidth this bit selects between a low or high input bandwidth. it is useful in limiting noise for lower frequency inputs. the power-up default setting is 1. low analog input bandwidth is ~100 mhz; high analog input bandwidth is ~200 mhz. table 43. input bandwidth select input bandwidth result 0 low analog input bandwidth 1 high analog input bandwidth 0x1e 4 power-down control select this bit sets whether power-down is controlled manually or automatically by the chip. if automatic control is selected (0x1e, bit 4), the ad9980s decision is based on the status of the sync detect bits (register 0x24, bits 2, 3, 6, and 7). if either an hsync or a sync- on-green input is detected on any input, the chip powers up, otherwise it powers down. if manual control is desired, the ad9980 includes flexibility of control with both a dedicated pin and a register bit. the dedicated pin allows a hardware watchdog circuit to control power-down, while the register bit allows
ad9980 preliminary technical data rev. 0 | page 34 of 44 power-down to be controlled by software. with manual power-down control, the polarity of the power-down pin must be set (0x1e, bit 2) whether it is used or not. if unused, it is recommended to set the polarity to active high and to hardwire the pin to ground with a 10 k? resistor. table 44. auto power-down select power-down select result 0 manual power-down control user determines power-down 1 auto power-down control chip determines power-down 0x1e 3 power-down this bit is used to manually put the chip in power- down mode. it is used only if manual power-down control is selected (see bit 4 of the power-down register). both the state of this register bit and the power-down pin (pin 17) are used to control manual power-down (see the power management section for more details on power-down.). table 45. power-down settings power-down select pin 17 result 0 0 normal operation 1 x power-down 0x1e 2 power-down polarity this bit defines the polarity of the power-down pin (pin 17). it is only used if manual power-down control is selected (see bit 4 above). table 46. power-down pin polarity select result 0 power-down pin is active low 1 power-down pin is active high 0x1e 1 power-down fast switching control this bit controls a special fast switching mode. with this bit, the ad9980 can stay active during power- down and only put the outputs in high impedance. this option is useful when the data outputs from two chips are connected on a pcb and the user wants to switch instantaneously between the two. table 47. power-down fast switching control fast switching control result 0 normal power-down operation 1 the chip stays powered-up and the outputs are put in high impedance mode 0x1e 0 sogout high impedance control this bit controls whether the sogout output pin is in high impedance or not when in power-down mode. in most cases, sogout is not put in high impedance during normal operation. it is usually needed for sync detection by the graphics controller. the option to put sogout in high impedance is included mainly to allow for factory testing modes. table 48. sogout high impedance control sogout control result 0 the sogout output operates as normal during power-down. 1 the sogout output is in high impedance during power-down. output control 0x1f 6:5 output mode these bits choose between three options for the output mode. in 4:4:4 mode rgb is standard, in 4:2:2 mode ycbcr is standard, which allows a reduction in the number of output pins from 24 to 16. in 4:4:4 ddr output mode, the data is in rgb mode but changes on every clock edge. the power-up default setting is 00. table 49. output mode output mode result 00 4:4:4 rgb mode 01 4:2:2 ycbcr mode 10 4:4:4 ddr mode 0x1f 4 primary output enable this bit places the primary output in active or high impedance mode. the power-up default setting is 1. table 50. primary output enable select result 0 primary output is in high impedance mode 1 primary output is enabled 0x1f 3 secondary output enable this bit places the secondary output in active or high impedance mode. the secondary output is designated when using either 4:2:2 or 4:4:4 ddr. in these modes, the data on the blue output channel is the secondary output while the output data on the red and green channels are the primary output. secondary output is always a ycbcr ddr data mode. see the output formatter section and table 11. the power-up default setting is 0. table 51. secondary output enable select result 0 secondary output is in high impedance mode 1 secondary output is enabled
ad9980 rev. 0 | page 35 of 44 0x1f 2:1 output drive strength these two bits select the drive strength for all high- speed digital outputs (except vsout, a0, and the o/e field). higher drive strength results in faster rise/fall times and in general makes it easier to capture data. lower drive strength results in slower rise/fall times and helps reduce emi and digitally generated power supply noise. the power-up default setting is 10. table 52. output drive strength output drive result 00 low output drive strength 01 medium low output drive strength 10 medium high output drive strength 11 high output drive strength 0x1f 0 output clock invert this bit allows inversion of the output clock. the power-up default setting is 0. table 53. output clock invert select result 0 noninverted pixel clock 1 inverted pixel clock 0x20 7:6 output clock select these bits allow selection of optional output clocks such as a fixed 40 mhz clock, a 2 clock, a 90 phase- shifted clock or the normal pixel clock. the power-up default setting is 00. table 54. output clock select select result 00 pixel clock 01 90 phase-shifted pixel clock 10 2 pixel clock 11 40 mhz internal clock 0x20 5 output high impedance this bit puts all outputs (except sogout) in a high impedance state. the power-up default setting is 0. table 55. output high impedance select result 0 normal outputs 1 all outputs (except sogout) in high impedance mode 0x20 4 sog high impedance this bit allows the sogout pin to be placed in high impedance mode. the power-up default setting is 0. table 56. sogout high impedance select result 0 normal sog output 1 sogout pin is in high impedance mode 0x20 3 field output polarity this bit sets the polarity of the field output bit. the power-up default setting is 1. table 57. field output polarity select result 0 active low = even field; active high = odd field 1 active low = odd field; active high = even field sync processing 0x20 2 pll sync filter this bit selects which signal the pll uses. it can select between either raw hsync or sog or filtered versions. the filtering of the hsync and sog can eliminate nearly all extraneous transitions which have tradi- tionally caused pll disruption. the power-up default setting is 0. table 58. pll sync filter enable select result 0 pll uses raw hsync or sog inputs 1 pll uses filtered hsync or sog inputs 0x20 1 sync processing input source this bit selects whether the sync processor uses a raw sync or a regenerated sync for the following functions: coast, h/v count, field detection and vsync duration counts. using the regenerated sync is recommended. table 59. sp filter enable select result 0 sync processing uses raw hsync or sog 1 sync processing uses the internally regenerated hsync 0x20 0 must be set to 1 for proper operation 0x21 7:0 must be set to default 0x22 7:0 must be set to default 0x23 7:0 sync filter window width this 8-bit register sets the window of time for the regenerated hsync leading edge (in 25 ns steps) when sync pulses are allowed to pass through. therefore with the default value of 10, the window width is 250 ns. the goal is to set the window width so that extraneous pulses are rejected. (see the sync processing section). as in the sync separator threshold, the 25 ns multiplier value is somewhat variable. the maximum variability over all operating conditions is 20% (20 ns to 30 ns).
ad9980 preliminary technical data rev. 0 | page 36 of 44 detection status 0x24 7 hsync0 detection bit this bit is used to indicate when activity is detected on the hsync0 input pin. if hsync is held high or low, activity will not be detected. the sync processing block diagram shows where this function is imple- mented. 0 = hsync0 is not active. 1 = hsync0 is active. table 60. hsync0 detection results detect result 0 no activity detected 1 activity detected 0x24 6 hsync1 detection bit this bit is used to indicate when activity is detected on the hsync1 input pin. if hsync is held high or low, activity is not detected. the sync processing block diagram shows where this function is implemented. 0 = hsync1 is not active. 1 = hsync1 is active. table 61. hsync1 detection results detect result 0 no activity detected 1 activity detected 0x24 5 vsync0 detection bit this bit is used to indicate when activity is detected on the vsync0 input pin. if vsync is held high or low, activity is not detected. the sync processing block diagram shows where this function is implemented. 0 = vsync0 not active. 1 = vsync0 is active. table 62. vsync0 detection results detect result 0 no activity detected 1 activity detected 0x24 4 vsync1 detection bit this bit is used to indicate when activity is detected on the vsync1 input pin. if vsync is held high or low, activity is not detected. the sync processing block diagram shows where this function is implemented. 0 = vsync1 is not active, 1 = vsync1 is active. table 63. vsync1 detection results detect result 0 no activity detected 1 activity detected 0x24 3 sog0 detection bit this bit is used to indicate when activity is detected on the sog0 input pin. if sog is held high or low, activity is not detected. the sync processing block diagram shows where this function is implemented. 0 = sog0 is not active. 1 = sog1 is active. table 64. sog0 detection results detect result 0 no activity detected 1 activity detected 0x24 2 sog1 detection bit this bit is used to indicate when activity is detected on the sog1 input pin. if sog is held high or low, activity is not detected. the sync processing block diagram shows where this function is implemented. 0 = sog1 not active. 1 = sog1 is active. table 65. sog1 detection results detect result 0 no activity detected 1 activity detected 0x24 1 coast detection bit this bit detects activity on the extclk/extcoast pin. it indicates one of the two signals is active, but it wont indicate if it is extclk or extcoast. a dc signal is not detected. table 66. coast detection result detect result 0 no activity detected 1 activity detected 0x24 0 clamp detection bit this bit is used to indicate when activity is detected on the external clamp pin. if external clamp is held high or low, activity is not detected. table 67. clamp detection results detect result 0 no activity detected 1 activity detected polarity status 0x25 7 hsync0 polarity indicates the polarity of hsync0 input. table 68. detected hsync0 polarity results detect result 0 hsync polarity is negative 1 hsync polarity is positive 0x25 6 hsync1 polarity indicates the polarity of hsync1 input. table 69. detected hsync1 polarity results detect result 0 hsync polarity is negative 1 hsync polarity is positive
ad9980 rev. 0 | page 37 of 44 0x25 5 vsync0 polarity indicates the polarity of vsync0 input. table 70. detected vsync0 polarity results detect result 0 vsync polarity is negative 1 vsync polarity is positive 0x25 4 vsync1 polarity indicates the polarity of vsync1 input. table 71. detected vsync1 polarity results detect result 0 vsync polarity is negative 1 vsync polarity is positive 0x25 3 coast polarity indicates the polarity of the external coast signal. table 72. detected coast polarity results detect result 0 coast polarity is negative 1 coast polarity is positive 0x25 2 clamp polarity indicates the polarity of the clamp signal. table 73. detected clamp polarity results detect result 0 clamp polarity is negative 1 clamp polarity is positive 0x25 1 extraneous pulses detection a second output from the hsync filter, this status bit tells whether extraneous pulses are present on the incoming sync signal. often extraneous pulses are used for copy protection, so this status bit can be used for this purpose. table 74. equalization pulse detect bit detect result 0 no equalization pulses detected during active hsync 1 equalization pulses detected during active hsync hsync count 0x26 7:0 hsyncs/vsync msb the 8 msbs of the 12-bit counter that reports the number of hsyncs/vsync on the active input. this is useful for determining the mode and is an aid in setting the pll divide ratio. 0x27 7:4 hsyncs/vsync lsbs the 4 lsbs of the 12-bit counter that reports the number of hsyncs/vsync on the active input. test registers 0x28 7:0 test register 1 must be written to 0xbf for proper operation. 0x29 7:0 test register 2 must be written to 0x00 for proper operation. 0x2a 7:0 test register 3 read only bits for future use. 0x2b 7:0 test register 4 read only bits for future use. 0x2c 7:5 must be written to 000 for proper operation. 0x2c 4 auto-offset hold a bit for controlling whether the auto-offset function runs continuously or runs once and holds the result. continuous updates are recommended because it allows the ad9980 to compensate for drift-over time, temperature, etc. if one-time updates are preferred, these should be performed every time the part is powered up and when there is a mode change. to do a one-time update, first auto-offset must be enabled (register 0x1b, bit 5). next, this bit (auto-offset hold) must first be set to 0 to let the auto-offset function operate and settle to a final value. auto-offset hold should then be set to 1 to hold the offset values that the auto circuitry calculates. the ad9980s auto-offset circuits maximum settle time is 10 updates. for example, if the update frequency is set to once every 64 hsyncs, then the maximum settling time would be 640 hsyncs (10 64 hsyncs). table 75. auto-offset hold select result 0 allows auto-offset to update continuously 1 disables auto-offset updates and holds the current auto-offset values 0x2c 3:0 must be written to 0x0 for proper operation. 0x2d 7:0 test register 5 read/write bits for future use. must be written to 0xe8 for proper operation. 0x2e 7:0 test register 6 read/write bits for future use. must be written to 0xe0 for proper operation.
ad9980 prelim inary technical data rev. 0 | page 38 of 44 two-wi re serial control port a tw o- wir e s e r i a l in t e r f ace co n t r o l in t e r f ace is pr o v ide d . u p t o tw o ad9980 de vices ma y b e conn ec t e d t o the tw o-wir e s e r i al in t e r f ace w i t h e a ch d e v i ce h a v i n g a uniq ue add r ess. the tw o - w i r e s e r i a l in ter f ace com p r i s e s a clo c k (scl) a nd a b i - dir e c t io na l d a t a p i n (sd a ). t h e a n a l o g f l a t p a nel in ter f ace ac ts a s a sla v e f o r r e ce i v i n g a n d tra n sm i t ti n g da t a o v e r th e se ri a l i n t e rf a c e . w h en th e se rial i n t e rf a c e i s n o t a c ti v e , th e l o gi c l e v e l s o n scl and sd a a r e p u l l e d hig h b y ext e r n al p u l l -u p r e sis t o r s. da t a r e cei v e d or tra n smi t t e d on the s d a lin e m u s t be s t ab le fo r th e d u ra ti o n o f th e posi t i v e g o in g sc l p u lse . d a ta o n s d a m u st cha n g e o n l y w h en scl is lo w . i f s d a chan g e s s t a t e w h i l e s c l is hig h , t h e s e r i a l i n t e r f ace i n t e r p rets t h a t ac t i o n a s a st a r t o r st o p seq u en c e . t h e f o l l ow i n g a r e t h e f i ve c o m p one n t s to s e r i a l bu s op e r a t i o n : ? st ar t s i g n a l ? sla v e a ddr ess b y te ? b a s e r e g i st er addr es s b y t e ? da t a b y t e t o r e ad o r wr i t e ? stop s i g n a l w h en t h e s e r i al in t e r f ace is i n ac t i v e (scl and s d a a r e hig h ), co mm uni c a t io n is ini t i a t e d b y s e ndin g a st a r t si g n a l . the st a r t sig n al is a hig h -t o-lo w tra n si tion o n s d a while scl is hig h . t h i s si gn al aler ts all s l a v ed de vices th a t a da t a t r a n sf er seq u en ce is co ming. the f i rst eig h t b i ts o f da t a t r a n sfer r e d a f t e r a st ar t sig n a l co m p r i s e a 7 - b i t sla ve addr ess (t h e f i rst s e ve n b i ts) a nd a si n g le r/w\ b i t (t h e ei g h t h b i t). t h e r / w\ b i t indic a te s t h e dir e c t io n of d a t a t r ans f e r : re a d f r om 1 or w r ite to 0 on t h e sl a v e d e v i c e . i f t h e t r a n s m i t t e d s l a v e addr es s ma t c h e s t h e addr e s s o f t h e de vice (s et b y t h e st a t e o f t h e s e r i al a0 addr es s [sa0] i n p u t pin in t a b l e 76), th e ad9980 ac k n o w ledg es t h e ma t c h b y b r in g i n g s d a lo w o n t h e nin t h scl p u ls e. i f t h e ad dr ess e s do n o t m a tch , th e ad9980 do es n o t ack n o w ledg e i t . table 76. serial port addresse s bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 a6 ( m s b ) a 5 a 4 a 3 a 2 a 1 a 0 1 0 0 1 1 0 0 1 0 0 1 1 0 1 data tra n sfer via se rial interface f o r eac h b y t e o f da ta r e ad o r wr i t t e n, t h e ms b is th e f i rs t b i t in th e s e q u en ce . i f th e ad9980 do es n o t ac k n o w ledg e t h e mas t er de vice d u r i n g a wr i t e s e q u e n ce , t h e sd a r e mains hig h s o t h e mas t er can g e n e r - a t e a s t o p sig n a l . i f t h e mas t er de v i ce do es n o t ackn o w le dge t h e ad9980 d u r i n g a r e ad s e q u enc e , th e ad9980 in t e r p r e ts this as end-o f - d a t a . t h e s d a r e m a in s hig h s o t h e m a ster ca n ge ner a te a st o p sig n a l . w r i t in g da t a t o s p ecif ic con t r o l r e g i s t ers o f th e ad9980 r e q u ir es t h a t t h e 8- b i t addr es s o f t h e con t r o l r e g i s t er o f in t e r e s t b e wr i t - t e n a f t e r t h e s l a v e addr es s has b e en es t a b l ish e d . this co n t r o l r e g i s t er addr es s is t h e b a s e addres s fo r s u bs e q ue n t wr i t e op era- tio n s. th e b a s e addr es s a u t o -incr e m e n t s b y o n e fo r e a c h b y t e o f d a t a wr i t te n a f ter t h e da t a b y te in te nde d fo r t h e b a s e ad dr ess. i f m o r e b y t e s a r e t r a n sfer r e d t h a n t h er e a r e a v a i lab l e addr ess e s, t h e a ddr ess wi l l n o t i n cr e m e n t and r e ma in s a t i t s max i m u m val u e o f 0x2e. a n y b a s e addr ess hig h er t h a n 0x2 e do es n o t p r o- d u ce an ack n o w le dge sig n a l . d a t a a r e r e ad f r o m t h e con t r o l r e g i s t ers o f th e ad9980 in a simila r mann er . readin g r e q u ir es tw o da t a t r a n sfe r o p era t io n s : the b a s e addr ess m u s t b e wr i t t e n w i t h t h e r/ w b i t o f t h e sla ve addr es s b y t e lo w t o s e t u p a s e q u en t i al r e ad op era t ion. re adi n g (t h e r / w\ b i t o f t h e sla v e addr es s b y t e hig h ) b e g i n s a t t h e p r e v i o u sly est a blish e d b a s e ad dr ess. the ad dr ess o f t h e r e ad re g i ste r a u to - i n c re me n t s af t e r e a ch by te i s t r a n s f e r re d. t o t e r m ina t e a read/wr i te s e q u en ce t o th e ad9 980, a s t o p sig n al m u s t be sen t . a s t o p s i gn al c o m p ri se s a l o w - t o -h i g h tra n si ti o n of sd a w h i l e s c l i s h i g h . a r e pea t ed s t a r t s i gn al occur s w h en th e m a s t e r d e v i ce d r i v in g t h e s e r i a l i n t e r f ace ge n e ra t e s a st a r t sig n a l w i t h o u t f i rst ge n e r - a t in g a st o p sig n a l t o t e r m ina t e t h e c u r r en t co m m unic a t ion. this is us e d t o cha n ge t h e m o d e o f co mm unic a t io n (r e a d , wr i t e) b e tw e e n t h e s l a v e a nd mas t er w i t h ou t r e le asing t h e s e r i al in t e r f ace li n e s . sda scl t buff t stah t dho t dsu t dal t dah t stasu t stosu 04740-010 f i gure 17. s e ri al p o r t r e ad/wri te t i mi ng
ad9980 rev. 0 | page 39 of 44 serial int e rf ac e re ad/write exampl es w r i t e t o o n e con t r o l r e g i s t er : ? st ar t s i g n a l ? sla v e a ddr ess b y te (r/ w \ b i t = lo w) ? ba se a d d r e s s b y t e ? d a t a b y te to b a s e a ddre s s ? stop s i g n a l w r i t e t o fo ur co n s e c u t i v e co n t rol r e g i s t ers: ? st ar t s i g n a l ? sla v e a ddr ess b y te (r/ w \ b i t = lo w) ? ba se a d d r e s s b y t e ? d a t a b y te to b a s e a ddre s s ? d a t a b y te to ( b a s e a ddre s s + 1 ) ? d a t a b y te to ( b a s e a ddre s s + 2 ) ? d a t a b y te to ( b a s e a ddre s s + 3 ) ? stop s i g n a l r e a d f r om on e c o n t ro l re g i ste r : ? st ar t s i g n a l ? sla v e addr es s b y t e (r/ w \ b i t = lo w) ? ba se a d d r e s s b y t e ? st ar t s i g n a l ? sla v e addr es s b y t e (r/ w \ b i t = hig h ) ? da t a b y t e f r o m ba se a d d r e s s ? stop s i g n a l read f r o m f o ur co n s ec u t i v e co n t r o l r e g i s t ers: ? st ar t s i g n a l ? sla v e addr es s b y t e (r/ w \ b i t = lo w) ? ba se a d d r e s s b y t e ? st ar t s i g n a l ? sla v e addr es s b y t e (r/ w \ b i t = hig h ) ? da t a b y t e f r o m ba se a d d r e s s ? d a t a b y t e f r o m (b as e ad dr ess + 1) ? d a t a b y t e f r o m (b as e ad dr ess + 2) ? d a t a b y t e f r o m (b as e ad dr ess + 3) ? stop s i g n a l bit 7 ack bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sda s cl 04740-011 f i g u re 18. s e ri al int e r f ace t y pi c a l b y t e t r ans f er
ad9980 rev. 0 | page 40 of 44 pcb layout recommendations the ad9980 is a high-precision, high-speed analog device. to achieve the maximum performance from the part, it is important to have a well laid-out board. the analog interface inputs section contains a guide for designing a board using the ad9980. analog interface inputs using the following layout techniques on the graphics inputs is extremely important: 1. minimize the trace length running into the graphics inputs. this is accomplished by placing the ad9980 as close as possible to the graphics vga connector. long input trace lengths are undesirable because they pick up noise from the board and other external sources. 2. place the 75 ? termination resistors (see figure 3) as close as possible to the ad9980 chip. any additional trace length between the termination resistors and the input of the ad9980 increases the magnitude of reflections, which corrupts the graphics signal. 3. use 75 ? matched impedance traces. trace impedances other than 75 ? also increases the chance of reflections. 4. the ad9980 has very high input bandwidth (200 mhz). while this is desirable for acquiring a high resolution pc graphics signal with fast edges, it also means that it captures any high frequency noise present. therefore, it is important to reduce the amount of noise that gets coupled to the inputs. avoid running any digital traces near the analog inputs. 5. due to the high bandwidth of the ad9980, sometimes low-pass filtering the analog inputs can help to reduce noise. (for many applications, filtering is unnecessary.) experiments have shown that placing a ferrite bead in series prior to the 75 ? termination resistor is helpful in filtering excess noise. specifically, the fair-rite #2508051217z0 was used, but an application could work best with a different bead value. alternatively, placing a 100 ? to 120 ? resistor between the 75 ? termination resistor and the input coupling capacitor is beneficial. power supply bypassing it is recommended to bypass each power supply pin with a 0.1 f capacitor. the exception is where two or more supply pins are adjacent to each other. for these groupings of powers/grounds, it is only necessary to have one bypass capacitor. the fundamental idea is to have a bypass capacitor within about 0.5 cm of each power pin. also, avoid placing the capacitor on the opposite side of the pc board from the ad9980, since that interposes resistive vias in the path. the bypass capacitors should be physically located between the power plane and the power pin. current should flow from the power plane > capacitor > power pin. do not make the power connection between the capacitor and the power pin. placing a via underneath the capacitor pads, down to the power plane, is generally the best approach. it is particularly important to maintain low noise and good stability of pv d (the clock generator supply). abrupt changes in pv d can result in similarly abrupt changes in sampling clock phase and frequency. this can be avoided by careful attention to regulation, filtering, and bypassing. it is highly desirable to provide separate regulated supplies for each of the analog circuitry groups (v d and pv d ). some graphic controllers use substantially different levels of power when active (during active picture time) and when idle (during horizontal and vertical sync periods). this can result in a measurable change in the voltage supplied to the analog supply regulator, which in turn can produce changes in the regulated analog supply voltage. this can be mitigated by regulating the analog supply, or at least pv d , from a different, cleaner, power source (for example, from a 12 v supply). it is also recommended to use a single ground plane for the entire board. experience has repeatedly shown that the noise performance is the same or better with a single ground plane. using multiple ground planes can be detrimental because each separate ground plane is smaller and long ground loops can result. in some cases, using separate ground planes is unavoidable. for those cases, it is recommended to at least place a single ground plane under the ad9980. the location of the split should be at the receiver of the digital outputs. in this case, it is even more important to place components wisely because the current loops will be much longer (current takes the path of least resistance). an example of a current loop is power plane to ad9980 to digital output trace to digital data receiver to digital ground plane to analog ground plane. pll place the pll loop filter components as close to the filt pin as possible. do not place any digital or other high frequency traces near these components. use the values suggested in the data- sheet with 10% tolerances or less. outputs (both data and clocks) try to minimize the trace length that the digital outputs have to drive. longer traces have higher capacitance and require more instantaneous current to drive, which creates more internal digital noise. shorter traces reduce the possibility of reflections.
ad9980 rev. 0 | page 41 of 44 adding a series resistor of value 50 ? to 200 ? can suppress reflections, reduce emi, and reduce the current spikes inside the ad9980. if series resistors are used, place them as close to the ad9980 pins as possible, (although try not to add vias or extra length to the output trace to get the resistors closer). if possible, limit the capacitance that each digital output drives to less than 10 pf. this is easily accomplished by keeping traces short and by connecting the outputs to only one device. loading the outputs with excessive capacitance increases the current transients inside of the ad9980 and creates more digital noise on its power supplies. digital inputs digital inputs on the ad9980 (hsync0, hsync1, vsync0, vsync1, sogin0, sogin1, sda, scl and clamp) were designed to work with 3.3 v signals, but are tolerant of 5.0 v signals. therefore, no extra components need to be added if using 5.0 v logic. any noise that gets onto the hsync input trace adds jitter to the system. therefore, minimize the trace length and do not run any digital or other high frequency traces near it. reference bypass the ad9980 has three reference voltages that must be bypassed for proper operation of the input pga. reflo and refhi are connected to each other through a 10 f capacitor. refcm is connected to ground through a 10 f capacitor. these refer- ences are used by the input pga circuitry to assure the greatest stability. place them as close to the ad9980 pin as possible. make the ground connection as short as possible.
ad9980 rev. 0 | page 42 of 44 outline dimensions 1.45 1.40 1.35 0.15 0.05 61 60 1 80 20 41 21 40 top view (pins down) pin 1 seating plane view a 1.60 max 0.75 0.60 0.45 0.20 0.09 0.10 max coplanarity view a rotated 90 ccw seating plane 10 6 2 7 3. 5 0 14.00 bsc sq 16.00 bsc sq 0.65 bsc 0.38 0.32 0.22 compliant to jedec standards ms-026-bec f i g u re 19. 8 0 -l ead l o w p r of i l e q u ad f l at p a ck [l qf p ] (st - 80-2) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature r a nge package descri ption package option AD9980KSTZ-80 1 0c to +70c 80-lead lqfp st-80-2 ad9980kstz-95 1 0c to +70c 80-lead lqfp st-80-2 a d 9 9 8 0 / p c b e v a l u a t i o n k i t 1 pb-fr ee part.
ad9980 rev. 0 | page 43 of 44 notes
ad9980 rev. 0 | page 44 of 44 notes pur chas e of l i cen s e d i 2 c co m p o n en ts o f ana l o g d e vic e s o r o n e o f i t s su blicen s e d a s s o cia t e d c o m p a n ies co n v e y s a licen s e f o r t h e pur c has e r un der t h e p h i li ps i 2 c p a t e n t righ ts t o us e t h es e com p on en ts in a n i 2 c s y s t em , p r o v id ed tha t th e s y s t e m c o n f o r m s t o th e i 2 c s t an d a r d s p e c if ica t io n as def i n e d b y p h i l i p s . ? 2005 a n al og d e vic e s , inc . a ll righ t s r e ser v ed . t r a d em arks and r e gist er e d tr adem ar ks ar e t h e proper t y of t h eir respec tiv e o w ners . d04740-0-1/05(0)

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